2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <arch/pirq_routing.h>
21 #include <console/console.h>
23 #include "../../../southbridge/amd/cs5536/cs5536.h"
32 #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
33 #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
34 #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
35 #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
38 #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
39 #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
40 #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
41 #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
44 * ALIX.2D3 interrupt wiring.
47 * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
48 * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
49 * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
50 * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
51 * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
52 * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
53 * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
54 * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
55 * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
57 * The only devices that interrupt are:
59 * What Device IRQ PIN PIN WIRED TO
60 * -------------------------------------------------
61 * AES 00:01.2 0a 01 A A
62 * eth0 00:09.0 0b 01 A B
63 * eth1 00:0a.0 0b 01 A C
64 * eth2 00:0b.0 0b 01 A D
65 * mpci 00:0c.0 0a 01 A A
66 * mpci 00:0c.0 0b 02 B B
67 * usb 00:0f.4 0b 04 D D
68 * usb 00:0f.5 0b 04 D D
70 * The only swizzled interrupts are the ethernet controllers, where INTA is wired to
71 * interrupt controller lines B, C and D.
74 const struct irq_routing_table intel_irq_routing_table = {
77 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
78 0x00, /* Where the interrupt router lies (bus) */
79 (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
80 0x00, /* IRQs devoted exclusively to PCI usage */
83 0, /* Miniport data */
84 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
87 /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
89 /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
92 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
94 /* On-board ethernet (Left) */
95 {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
97 /* On-board ethernet (Middle, ALIX.2D3 only) */
98 {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
100 /* On-board ethernet (Right) */
101 {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
103 /* Mini PCI (slot 1) */
104 {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
106 /* Mini PCI (slot 2, ALIX.2D2 only) */
107 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
109 /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
110 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
114 unsigned long write_pirq_routing_table(unsigned long addr)
116 return copy_pirq_routing_table(addr);