src/mainboard/pcengines/alix1c/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com>
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; either version 2 of the License, or
   9 ## (at your option) any later version.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16 ## You should have received a copy of the GNU General Public License
  17 ## along with this program; if not, write to the Free Software
  18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19 ##
  20
  21 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  22 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  23 include /config/nofailovercalculation.lb
  24
  25 ##
  26 ## Set all of the defaults for an x86 architecture
  27 ##
  28
  29 arch i386 end
  30
  31 ##
  32 ## Build the objects we have code for in this directory.
  33 ##
  34
  35 driver mainboard.o
  36
  37 if CONFIG_GENERATE_PIRQ_TABLE
  38         object irq_tables.o
  39 end
  40
  41         #compile cache_as_ram.c to auto.inc
  42         makerule ./cache_as_ram_auto.inc
  43                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  44                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  45                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  46                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  47         end
  48
  49 ##
  50 ## Build our 16 bit and 32 bit coreboot entry code
  51 ##
  52 mainboardinit cpu/x86/16bit/entry16.inc
  53 mainboardinit cpu/x86/32bit/entry32.inc
  54 ldscript /cpu/x86/16bit/entry16.lds
  55 ldscript /cpu/x86/32bit/entry32.lds
  56
  57 ##
  58 ## Build our reset vector (This is where coreboot is entered)
  59 ##
  60 if CONFIG_USE_FALLBACK_IMAGE
  61         mainboardinit cpu/x86/16bit/reset16.inc
  62         ldscript /cpu/x86/16bit/reset16.lds
  63 else
  64         mainboardinit cpu/x86/32bit/reset32.inc
  65         ldscript /cpu/x86/32bit/reset32.lds
  66 end
  67
  68 ### Should this be in the northbridge code?
  69 mainboardinit arch/i386/lib/cpu_reset.inc
  70
  71 ##
  72 ## Include an id string (For safe flashing)
  73 ##
  74 mainboardinit arch/i386/lib/id.inc
  75 ldscript /arch/i386/lib/id.lds
  76
  77 ###
  78 ### This is the early phase of coreboot startup
  79 ### Things are delicate and we test to see if we should
  80 ### failover to another image.
  81 ###
  82 if CONFIG_USE_FALLBACK_IMAGE
  83         ldscript /arch/i386/lib/failover.lds
  84 #       mainboardinit ./failover.inc
  85 end
  86
  87 ###
  88 ### O.k. We aren't just an intermediary anymore!
  89 ###
  90
  91 ##
  92 ## Setup RAM
  93 ##
  94 mainboardinit cpu/x86/fpu/enable_fpu.inc
  95
  96         mainboardinit cpu/amd/model_lx/cache_as_ram.inc
  97         mainboardinit ./cache_as_ram_auto.inc
  98
  99 ##
 100 ## Include the secondary Configuration files
 101 ##
 102 dir /pc80
 103 config chip.h
 104
 105 chip northbridge/amd/lx
 106         device pci_domain 0 on
 107                 device pci 1.0 on end
 108                 device pci 1.1 on end
 109                 chip southbridge/amd/cs5536
 110                         # IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
 111                         # SIRQ Mode = Active(Quiet) mode. Save power....
 112                         # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
 113                         # How to get these? Boot linux and do this:
 114                         # rdmsr 0x51400025
 115                         register "lpc_serirq_enable" = "0x0000105a"
 116                         # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
 117                         register "lpc_serirq_polarity" = "0x0000EFA5"
 118                         # mode is high 10 bits (determined from code)
 119                         register "lpc_serirq_mode" = "1"
 120                         # Don't yet know how to find this.
 121                         register "enable_gpio_int_route" = "0x0D0C0700"
 122                         register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
 123                         register "enable_USBP4_device" = "0"    #0: host, 1:device
 124                         register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
 125                         register "com1_enable" = "0"
 126                         register "com1_address" = "0x3F8"
 127                         register "com1_irq" = "4"
 128                         register "com2_enable" = "0"
 129                         register "com2_address" = "0x2F8"
 130                         register "com2_irq" = "3"
 131                         register "unwanted_vpci[0]" = "0"       # End of list has a zero
 132                                 device pci f.0 on       # ISA Bridge
 133                                 chip superio/winbond/w83627hf
 134                                         device pnp 2e.0 off #  Floppy
 135                                                 io 0x60 = 0x3f0
 136                                                 irq 0x70 = 6
 137                                                 drq 0x74 = 2
 138                                         end
 139                                         device pnp 2e.1 on #  Parallel Port
 140                                                 io 0x60 = 0x378
 141                                                 irq 0x70 = 7
 142                                         end
 143                                         device pnp 2e.2 on #  Com1
 144                                                 io 0x60 = 0x3f8
 145                                                 irq 0x70 = 4
 146                                         end
 147                                         device pnp 2e.3 on #  Com2
 148                                                 io 0x60 = 0x2f8
 149                                                 irq 0x70 = 3
 150                                         end
 151                                         device pnp 2e.5 on #  Keyboard
 152                                                 io 0x60 = 0x60
 153                                                 io 0x62 = 0x64
 154                                                 irq 0x70 = 1
 155                                                 irq 0x72 = 12
 156                                         end
 157                                         device pnp 2e.6 off #  CIR
 158                                                 io 0x60 = 0x100
 159                                         end
 160                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 161                                                 io 0x60 = 0x220
 162                                                 io 0x62 = 0x300
 163                                                 irq 0x70 = 9
 164                                         end
 165                                         device pnp 2e.8 on end #  GPIO2
 166                                         device pnp 2e.9 on end #  GPIO3
 167                                         device pnp 2e.a on end #  ACPI
 168                                         device pnp 2e.b on #  HW Monitor
 169                                                 io 0x60 = 0x290
 170                                                 irq 0x70 = 5
 171                                         end
 172                                 end
 173                         end
 174                         device pci f.1 on end   # Flash controller
 175                         device pci f.2 on end   # IDE controller
 176                                 device pci f.3 on end   # Audio
 177                                 device pci f.4 on end   # OHCI
 178                         device pci f.5 on end   # EHCI
 179                 end
 180         end
 181
 182         # APIC cluster is late CPU init.
 183         device apic_cluster 0 on
 184                 chip cpu/amd/model_lx
 185                         device apic 0 on end
 186                 end
 187         end
 188
 189 end
 190