1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
17 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
24 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
25 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
28 makerule ./failover.inc
29 depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
30 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
34 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
35 action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
38 depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
39 action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
43 ## Build our 16 bit and 32 bit coreboot entry code
45 mainboardinit cpu/x86/16bit/entry16.inc
46 mainboardinit cpu/x86/32bit/entry32.inc
47 ldscript /cpu/x86/16bit/entry16.lds
48 ldscript /cpu/x86/32bit/entry32.lds
51 ## Build our reset vector (This is where coreboot is entered)
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/reset16.inc
55 ldscript /cpu/x86/16bit/reset16.lds
57 mainboardinit cpu/x86/32bit/reset32.inc
58 ldscript /cpu/x86/32bit/reset32.lds
61 ### Should this be in the northbridge code?
62 mainboardinit arch/i386/lib/cpu_reset.inc
65 ## Include an id string (For safe flashing)
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
71 ### This is the early phase of coreboot startup
72 ### Things are delicate and we test to see if we should
73 ### failover to another image.
75 if CONFIG_USE_FALLBACK_IMAGE
76 ldscript /arch/i386/lib/failover.lds
77 mainboardinit ./failover.inc
81 ### O.k. We aren't just an intermediary anymore!
87 mainboardinit cpu/x86/fpu/enable_fpu.inc
88 mainboardinit ./auto.inc
91 ## Include the secondary Configuration files
96 chip northbridge/amd/gx2
97 register "irqmap" = "0xaa5b"
98 register "setupflash" = "0"
99 device apic_cluster 0 on
100 chip cpu/amd/model_gx2
104 device pci_domain 0 on
105 device pci 1.0 on end
106 device pci 1.1 on end
107 chip southbridge/amd/cs5536
108 # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
109 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
110 # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
111 # Frame Pulse Width = 4clocks
112 # IRQ Data Frames = 17Frames
113 # SIRQ Mode = continous , It would be better if the EC could operate in
114 # Active(Quiet) mode. Save power....
115 # SIRQ Enable = Enabled
116 # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
117 #register "lpc_irq" = "0x00001002"
118 #register "lpc_serirq_enable" = "0xEFFD0080"
119 #register "enable_gpio0_inta" = "1"
120 #register "enable_ide_nand_flash" = "1"
121 #register "enable_uarta" = "1"
122 #register "enable_USBP4_host" = "1"
123 #register "audio_irq" = "5"
124 #register "usbf4_irq" = "10"
125 #register "usbf5_irq" = "10"
126 #register "usbf6_irq" = "0"
127 #register "usbf7_irq" = "0"
128 device pci d.0 on end # Realtek 8139 LAN
129 device pci f.0 on end # ISA Bridge
130 device pci f.2 on end # IDE Controller
131 device pci f.3 on end # Audio
132 device pci f.4 on end # OHCI
133 device pci f.5 on end # EHCI
134 register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
135 register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
136 register "unwanted_vpci[2]" = "0" # End of list has a zero