1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_HAVE_OPTION_TABLE
8 uses CONFIG_USE_OPTION_TABLE
9 uses CONFIG_ROM_PAYLOAD
10 uses CONFIG_IRQ_SLOT_COUNT
12 uses CONFIG_MAINBOARD_VENDOR
13 uses CONFIG_MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
16 uses CONFIG_FALLBACK_SIZE
17 uses CONFIG_STACK_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_IMAGE_SIZE
22 uses CONFIG_ROM_SECTION_SIZE
23 uses CONFIG_ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
26 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
28 uses CONFIG_PAYLOAD_SIZE
31 uses CONFIG_XIP_ROM_SIZE
32 uses CONFIG_XIP_ROM_BASE
33 uses CONFIG_HAVE_MP_TABLE
34 uses CONFIG_CROSS_COMPILE
38 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
39 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
40 uses CONFIG_CONSOLE_SERIAL8250
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_UDELAY_TSC
45 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
47 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
48 default CONFIG_ROM_SIZE = 256*1024
55 ## Build code for the fallback boot
57 default CONFIG_HAVE_FALLBACK_BOOT=1
62 default CONFIG_HAVE_MP_TABLE=0
65 ## Build code to reset the motherboard from coreboot
67 default CONFIG_HAVE_HARD_RESET=0
69 ## Delay timer options
71 default CONFIG_UDELAY_TSC=1
72 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
75 ## Build code to export a programmable irq routing table
77 default CONFIG_HAVE_PIRQ_TABLE=1
78 default CONFIG_IRQ_SLOT_COUNT=2
82 ## Build code to export a CMOS option table
84 default CONFIG_HAVE_OPTION_TABLE=0
87 ### coreboot layout values
90 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
91 default CONFIG_ROM_IMAGE_SIZE = 65536
92 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
95 ## Use a small 8K stack
97 default CONFIG_STACK_SIZE=0x2000
100 ## Use a small 16K heap
102 default CONFIG_HEAP_SIZE=0x4000
105 ## Only use the option table in a normal image
107 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
108 default CONFIG_USE_OPTION_TABLE = 0
110 default CONFIG_RAMBASE = 0x00004000
112 default CONFIG_ROM_PAYLOAD = 1
115 ## The default compiler
117 default CONFIG_CROSS_COMPILE=""
118 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
122 ## The Serial Console
125 # To Enable the Serial Console
126 default CONFIG_CONSOLE_SERIAL8250=1
128 ## Select the serial console baud rate
129 default CONFIG_TTYS0_BAUD=115200
130 #default CONFIG_TTYS0_BAUD=57600
131 #default CONFIG_TTYS0_BAUD=38400
132 #default CONFIG_TTYS0_BAUD=19200
133 #default CONFIG_TTYS0_BAUD=9600
134 #default CONFIG_TTYS0_BAUD=4800
135 #default CONFIG_TTYS0_BAUD=2400
136 #default CONFIG_TTYS0_BAUD=1200
138 # Select the serial console base port
139 default CONFIG_TTYS0_BASE=0x3f8
141 # Select the serial protocol
142 # This defaults to 8 data bits, 1 stop bit, and no parity
143 default CONFIG_TTYS0_LCS=0x3
146 ### Select the coreboot loglevel
148 ## EMERG 1 system is unusable
149 ## ALERT 2 action must be taken immediately
150 ## CRIT 3 critical conditions
151 ## ERR 4 error conditions
152 ## WARNING 5 warning conditions
153 ## NOTICE 6 normal but significant condition
154 ## INFO 7 informational
155 ## CONFIG_DEBUG 8 debug-level messages
156 ## SPEW 9 Way too many details
158 ## Request this level of debugging output
159 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
160 ## At a maximum only compile in this level of debugging
161 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
168 default CONFIG_CBFS=1