src/mainboard/nvidia/l1_2pvv/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #if CONFIG_K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36 #include <usbdebug.h>
  37 #include <lib.h>
  38 #include <spd.h>
  39 #include <cpu/amd/model_fxx_rev.h>
  40 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  41 #include "northbridge/amd/amdk8/raminit.h"
  42 #include "cpu/amd/model_fxx/apic_timer.c"
  43 #include "lib/delay.c"
  44 #include "cpu/x86/lapic/boot_cpu.c"
  45 #include "northbridge/amd/amdk8/reset_test.c"
  46 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  47 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
  48 #include "cpu/x86/bist.h"
  49 #include "northbridge/amd/amdk8/debug.c"
  50 #include "cpu/x86/mtrr/earlymtrr.c"
  51 #include "northbridge/amd/amdk8/setup_resource_map.c"
  52 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  53
  54 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  55
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #include "northbridge/amd/amdk8/amdk8_f.h"
  71 #include "northbridge/amd/amdk8/incoherent_ht.c"
  72 #include "northbridge/amd/amdk8/coherent_ht.c"
  73 #include "northbridge/amd/amdk8/raminit_f.c"
  74 #include "lib/generic_sdram.c"
  75 #include "resourcemap.c"
  76 #include "cpu/amd/dualcore/dualcore.c"
  77
  78 #define MCP55_MB_SETUP \
  79         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  80         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  81         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  82         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  83         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  84         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  85
  86 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  87 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90 #include "cpu/amd/model_fxx/fidvid.c"
  91 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 static void sio_setup(void)
  95 {
  96         uint32_t dword;
  97         uint8_t byte;
  98
  99         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 100         byte |= 0x20;
 101         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 102
 103         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 104         dword |= (1<<0);
 105         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 106
 107         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 108         dword |= (1<<16);
 109         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 110 }
 111
 112 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 113 {
 114         static const uint16_t spd_addr [] = {
 115                         // Node 0
 116                         DIMM0, DIMM2, 0, 0,
 117                         DIMM1, DIMM3, 0, 0,
 118                         // Node 1
 119                         DIMM4, DIMM6, 0, 0,
 120                         DIMM5, DIMM7, 0, 0,
 121         };
 122
 123         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 124                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 125
 126         int needs_reset = 0;
 127         unsigned bsp_apicid = 0;
 128
 129         if (!cpu_init_detectedx && boot_cpu()) {
 130                 /* Nothing special needs to be done to find bus 0 */
 131                 /* Allow the HT devices to be found */
 132
 133                 enumerate_ht_chain();
 134
 135                 sio_setup();
 136
 137                 /* Setup the mcp55 */
 138                 mcp55_enable_rom();
 139         }
 140
 141         if (bist == 0) {
 142                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 143         }
 144
 145         pnp_enter_ext_func_mode(SERIAL_DEV);
 146         pnp_write_config(SERIAL_DEV, 0x24, 0);
 147         w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 148         pnp_exit_ext_func_mode(SERIAL_DEV);
 149
 150         setup_mb_resource_map();
 151
 152         uart_init();
 153
 154         /* Halt if there was a built in self test failure */
 155         report_bist_failure(bist);
 156
 157 #if CONFIG_USBDEBUG
 158         mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 159         early_usbdebug_init();
 160 #endif
 161         console_init();
 162         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 163
 164         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 165
 166 #if CONFIG_MEM_TRAIN_SEQ == 1
 167         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 168 #endif
 169         setup_coherent_ht_domain(); // routing table and start other core0
 170
 171         wait_all_core0_started();
 172 #if CONFIG_LOGICAL_CPUS==1
 173         // It is said that we should start core1 after all core0 launched
 174         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 175          * So here need to make sure last core0 is started, esp for two way system,
 176          * (there may be apic id conflicts in that case)
 177          */
 178         start_other_cores();
 179         wait_all_other_cores_started(bsp_apicid);
 180 #endif
 181
 182         /* it will set up chains and store link pair for optimization later */
 183         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 184
 185 #if CONFIG_SET_FIDVID
 186
 187         {
 188                 msr_t msr;
 189                 msr=rdmsr(0xc0010042);
 190                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 191
 192         }
 193
 194         enable_fid_change();
 195
 196         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 197
 198         init_fidvid_bsp(bsp_apicid);
 199
 200         // show final fid and vid
 201         {
 202                 msr_t msr;
 203                 msr=rdmsr(0xc0010042);
 204                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 205
 206         }
 207 #endif
 208         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 209
 210         needs_reset |= optimize_link_coherent_ht();
 211         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 212         needs_reset |= mcp55_early_setup_x();
 213
 214         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 215         if (needs_reset) {
 216                 print_info("ht reset -\n");
 217                 soft_reset();
 218         }
 219         allow_all_aps_stop(bsp_apicid);
 220
 221         //It's the time to set ctrl in sysinfo now;
 222         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 223
 224         enable_smbus();
 225
 226         /* all ap stopped? */
 227
 228         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 229
 230         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 231 }