2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 uses USE_FALLBACK_IMAGE
29 uses USE_FAILOVER_IMAGE
30 uses HAVE_FALLBACK_BOOT
31 uses HAVE_FAILOVER_BOOT
34 uses HAVE_OPTION_TABLE
36 uses CONFIG_MAX_PHYSICAL_CPUS
37 uses CONFIG_LOGICAL_CPUS
46 uses ROM_SECTION_OFFSET
47 uses CONFIG_ROM_PAYLOAD
48 uses CONFIG_ROM_PAYLOAD_START
49 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
50 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
51 uses CONFIG_PRECOMPRESSED_PAYLOAD
59 uses LB_CKS_RANGE_START
62 uses MAINBOARD_PART_NUMBER
65 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
66 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
67 uses COREBOOT_EXTRA_VERSION
72 uses DEFAULT_CONSOLE_LOGLEVEL
73 uses MAXIMUM_CONSOLE_LOGLEVEL
74 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
75 uses CONFIG_CONSOLE_SERIAL8250
83 uses CONFIG_CONSOLE_VGA
84 uses CONFIG_USBDEBUG_DIRECT
85 uses CONFIG_PCI_ROM_RUN
86 uses HW_MEM_HOLE_SIZEK
87 uses HW_MEM_HOLE_SIZE_AUTO_INC
88 uses K8_HT_FREQ_1G_SUPPORT
90 uses HT_CHAIN_UNITID_BASE
91 uses HT_CHAIN_END_UNITID_BASE
92 uses SB_HT_CHAIN_ON_BUS0
93 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
98 uses DCACHE_RAM_GLOBAL_VAR_SIZE
103 uses ENABLE_APIC_EXT_ID
105 uses LIFT_BSP_APIC_ID
107 uses CONFIG_PCI_64BIT_PREF_MEM
109 uses CONFIG_LB_MEM_TOPK
111 uses CONFIG_AP_CODE_IN_CAR
115 uses WAIT_BEFORE_CPUS_INIT
117 uses CONFIG_USE_PRINTK_IN_CAR
124 ## ROM_SIZE is the size of boot ROM that this board will use.
126 default ROM_SIZE=524288
127 #default ROM_SIZE=0x100000
130 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
132 #default FALLBACK_SIZE=131072
133 #default FALLBACK_SIZE=0x40000
136 default FALLBACK_SIZE=0x3f000
138 default FAILOVER_SIZE=0x01000
141 default CONFIG_LB_MEM_TOPK=2048
144 ## Build code for the fallback boot
146 default HAVE_FALLBACK_BOOT=1
147 default HAVE_FAILOVER_BOOT=1
150 ## Build code to reset the motherboard from coreboot
152 default HAVE_HARD_RESET=1
155 ## Build code to export a programmable irq routing table
157 default HAVE_PIRQ_TABLE=1
158 default IRQ_SLOT_COUNT=11
161 ## Build code to export an x86 MP table
162 ## Useful for specifying IRQ routing values
164 default HAVE_MP_TABLE=1
166 ## ACPI tables will be included
167 default HAVE_ACPI_TABLES=0
170 ## Build code to export a CMOS option table
172 default HAVE_OPTION_TABLE=1
175 ## Move the default coreboot cmos range off of AMD RTC registers
177 default LB_CKS_RANGE_START=49
178 default LB_CKS_RANGE_END=122
179 default LB_CKS_LOC=123
182 ## Build code for SMP support
183 ## Only worry about 2 micro processors
186 default CONFIG_MAX_CPUS=4
187 default CONFIG_MAX_PHYSICAL_CPUS=2
188 default CONFIG_LOGICAL_CPUS=1
190 #default SERIAL_CPU_INIT=0
192 default ENABLE_APIC_EXT_ID=0
193 default APIC_ID_OFFSET=0x10
194 default LIFT_BSP_APIC_ID=1
196 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
198 #default HW_MEM_HOLE_SIZEK=0x200000
200 default HW_MEM_HOLE_SIZEK=0x100000
202 #default HW_MEM_HOLE_SIZEK=0x80000
204 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
205 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
207 #Opteron K8 1G HT Support
208 default K8_HT_FREQ_1G_SUPPORT=1
211 default CONFIG_CONSOLE_VGA=1
212 default CONFIG_PCI_ROM_RUN=1
214 #default CONFIG_USBDEBUG_DIRECT=1
216 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
217 default HT_CHAIN_UNITID_BASE=0
219 #real SB Unit ID, default is 0x20, mean dont touch it at last
220 #default HT_CHAIN_END_UNITID_BASE=0x6
222 #make the SB HT chain on bus 0, default is not (0)
223 default SB_HT_CHAIN_ON_BUS0=2
225 #only offset for SB chain?, default is yes(1)
226 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
228 #allow capable device use that above 4G
229 #default CONFIG_PCI_64BIT_PREF_MEM=1
232 ## enable CACHE_AS_RAM specifics
234 default USE_DCACHE_RAM=1
235 default DCACHE_RAM_BASE=0xc8000
236 default DCACHE_RAM_SIZE=0x08000
237 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
238 default CONFIG_USE_INIT=0
240 default CONFIG_AP_CODE_IN_CAR=0
241 default MEM_TRAIN_SEQ=1
242 default WAIT_BEFORE_CPUS_INIT=1
245 ## Build code to setup a generic IOAPIC
247 default CONFIG_IOAPIC=1
250 ## Clean up the motherboard id strings
252 default MAINBOARD_PART_NUMBER="l1_2pvv"
253 default MAINBOARD_VENDOR="NVIDIA"
254 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
255 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
258 ### coreboot layout values
261 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
262 default ROM_IMAGE_SIZE = 65536
265 ## Use a small 8K stack
267 default STACK_SIZE=0x2000
270 ## Use a small 32K heap
272 default HEAP_SIZE=0x8000
275 ## Only use the option table in a normal image
277 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
280 ## Coreboot C code runs at this location in RAM
282 default _RAMBASE=0x00100000
285 ## Load the payload from the ROM
287 default CONFIG_ROM_PAYLOAD = 1
289 #default CONFIG_COMPRESSED_PAYLOAD = 1
292 ### Defaults of options that you may want to override in the target config file
296 ## The default compiler
298 default CC="$(CROSS_COMPILE)gcc -m32"
302 ## Disable the gdb stub by default
304 default CONFIG_GDB_STUB=0
307 ## The Serial Console
309 default CONFIG_USE_PRINTK_IN_CAR=1
311 # To Enable the Serial Console
312 default CONFIG_CONSOLE_SERIAL8250=1
314 ## Select the serial console baud rate
315 default TTYS0_BAUD=115200
316 #default TTYS0_BAUD=57600
317 #default TTYS0_BAUD=38400
318 #default TTYS0_BAUD=19200
319 #default TTYS0_BAUD=9600
320 #default TTYS0_BAUD=4800
321 #default TTYS0_BAUD=2400
322 #default TTYS0_BAUD=1200
324 # Select the serial console base port
325 default TTYS0_BASE=0x3f8
327 # Select the serial protocol
328 # This defaults to 8 data bits, 1 stop bit, and no parity
329 default TTYS0_LCS=0x3
332 ### Select the coreboot loglevel
334 ## EMERG 1 system is unusable
335 ## ALERT 2 action must be taken immediately
336 ## CRIT 3 critical conditions
337 ## ERR 4 error conditions
338 ## WARNING 5 warning conditions
339 ## NOTICE 6 normal but significant condition
340 ## INFO 7 informational
341 ## DEBUG 8 debug-level messages
342 ## SPEW 9 Way too many details
344 ## Request this level of debugging output
345 default DEFAULT_CONSOLE_LOGLEVEL=8
346 ## At a maximum only compile in this level of debugging
347 default MAXIMUM_CONSOLE_LOGLEVEL=8
350 ## Select power on after power fail setting
351 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
358 default CONFIG_ROMFS=0