nvidia/mcp55: Move HAVE_HARD_RESET to southbridge
[coreboot.git] / src / mainboard / nvidia / l1_2pvv / Kconfig
1 if BOARD_NVIDIA_L1_2PVV
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_F
7         select DIMM_DDR2
8         select DIMM_REGISTERED
9         select NORTHBRIDGE_AMD_AMDK8
10         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
11         select SOUTHBRIDGE_NVIDIA_MCP55
12         select MCP55_USE_NIC
13         select MCP55_USE_AZA
14         select SUPERIO_WINBOND_W83627EHG
15         select HAVE_OPTION_TABLE
16         select HAVE_BUS_CONFIG
17         select HAVE_PIRQ_TABLE
18         select HAVE_MP_TABLE
19         select LIFT_BSP_APIC_ID
20         select K8_REV_F_SUPPORT
21         select BOARD_ROMSIZE_KB_512
22         select RAMINIT_SYSINFO
23         select QRANK_DIMM_SUPPORT
24         select K8_ALLOCATE_IO_RANGE
25
26 config MAINBOARD_DIR
27         string
28         default nvidia/l1_2pvv
29
30 config DCACHE_RAM_BASE
31         hex
32         default 0xc8000
33
34 config DCACHE_RAM_SIZE
35         hex
36         default 0x08000
37
38 config DCACHE_RAM_GLOBAL_VAR_SIZE
39         hex
40         default 0x01000
41
42 config APIC_ID_OFFSET
43         hex
44         default 0x10
45
46 config MEM_TRAIN_SEQ
47         int
48         default 1
49
50 config MCP55_NUM
51         int
52         default 2
53
54 config SB_HT_CHAIN_ON_BUS0
55         int
56         default 2
57
58 config MAINBOARD_PART_NUMBER
59         string
60         default "l1_2pvv"
61
62 config PCI_64BIT_PREF_MEM
63         bool
64         default n
65
66 config MAX_CPUS
67         int
68         default 4
69
70 config MAX_PHYSICAL_CPUS
71         int
72         default 2
73
74 config HT_CHAIN_UNITID_BASE
75         hex
76         default 0x0
77
78 config HT_CHAIN_END_UNITID_BASE
79         hex
80         default 0x20
81
82 config SERIAL_CPU_INIT
83         bool
84         default n
85
86 config IRQ_SLOT_COUNT
87         int
88         default 11
89
90 config MCP55_PCI_E_X_0
91         int
92         default 2
93
94 endif # BOARD_NVIDIA_L1_2PVV