src/mainboard/nvidia/l1_2pvv/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/failovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 #needed by irq_tables and mptable and acpi_tables
  34 object get_bus_conf.o
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  38 #object reset.o
  39
  40 if CONFIG_GENERATE_ACPI_TABLES
  41         object acpi_tables.o
  42         object fadt.o
  43         makerule dsdt.c
  44                 depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
  45                 action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
  46                 action  "mv dsdt_lb.hex dsdt.c"
  47         end
  48         object ./dsdt.o
  49
  50         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  51
  52         if CONFIG_ACPI_SSDTX_NUM
  53             makerule ssdt6.c
  54                         depends "$(CONFIG_MAINBOARD)/dx/pci6.asl"
  55                         action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl"
  56                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
  57                         action  "mv pci6.hex ssdt6.c"
  58             end
  59             object ./ssdt6.o
  60             makerule ssdt5.c
  61                         depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
  62                         action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
  63                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
  64                         action  "mv pci5.hex ssdt5.c"
  65             end
  66             object ./ssdt5.o
  67         end
  68 end
  69
  70         if CONFIG_USE_INIT
  71                 makerule ./cache_as_ram_auto.o
  72                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  73                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  74                 end
  75         else
  76                 makerule ./cache_as_ram_auto.inc
  77                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  78                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  79                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  80                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  81                 end
  82         end
  83
  84 if CONFIG_USE_FAILOVER_IMAGE
  85 else
  86     if CONFIG_AP_CODE_IN_CAR
  87         makerule ./apc_auto.o
  88                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  89                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  90         end
  91         ldscript /arch/i386/init/ldscript_apc.lb
  92     end
  93 end
  94
  95
  96 ##
  97 ## Build our 16 bit and 32 bit coreboot entry code
  98 ##
  99 if CONFIG_HAVE_FAILOVER_BOOT
 100     if CONFIG_USE_FAILOVER_IMAGE
 101         mainboardinit cpu/x86/16bit/entry16.inc
 102         ldscript /cpu/x86/16bit/entry16.lds
 103     end
 104 else
 105     if CONFIG_USE_FALLBACK_IMAGE
 106         mainboardinit cpu/x86/16bit/entry16.inc
 107         ldscript /cpu/x86/16bit/entry16.lds
 108     end
 109 end
 110
 111 mainboardinit cpu/x86/32bit/entry32.inc
 112
 113         if CONFIG_USE_INIT
 114                 ldscript /cpu/x86/32bit/entry32.lds
 115         end
 116
 117         if CONFIG_USE_INIT
 118                 ldscript /cpu/amd/car/cache_as_ram.lds
 119         end
 120
 121 ##
 122 ## Build our reset vector (This is where coreboot is entered)
 123 ##
 124 if CONFIG_HAVE_FAILOVER_BOOT
 125     if CONFIG_USE_FAILOVER_IMAGE
 126         mainboardinit cpu/x86/16bit/reset16.inc
 127         ldscript /cpu/x86/16bit/reset16.lds
 128     else
 129         mainboardinit cpu/x86/32bit/reset32.inc
 130         ldscript /cpu/x86/32bit/reset32.lds
 131     end
 132 else
 133     if CONFIG_USE_FALLBACK_IMAGE
 134         mainboardinit cpu/x86/16bit/reset16.inc
 135         ldscript /cpu/x86/16bit/reset16.lds
 136     else
 137         mainboardinit cpu/x86/32bit/reset32.inc
 138         ldscript /cpu/x86/32bit/reset32.lds
 139     end
 140 end
 141
 142 ##
 143 ## Include an id string (For safe flashing)
 144 ##
 145 mainboardinit southbridge/nvidia/mcp55/id.inc
 146 ldscript /southbridge/nvidia/mcp55/id.lds
 147
 148 ##
 149 ## ROMSTRAP table for MCP55
 150 ##
 151 if CONFIG_HAVE_FAILOVER_BOOT
 152     if CONFIG_USE_FAILOVER_IMAGE
 153         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 154         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 155     end
 156 else
 157     if CONFIG_USE_FALLBACK_IMAGE
 158         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 159         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 160     end
 161 end
 162
 163         ##
 164         ## Setup Cache-As-Ram
 165         ##
 166         mainboardinit cpu/amd/car/cache_as_ram.inc
 167
 168 ###
 169 ### This is the early phase of coreboot startup
 170 ### Things are delicate and we test to see if we should
 171 ### failover to another image.
 172 ###
 173 if CONFIG_HAVE_FAILOVER_BOOT
 174     if CONFIG_USE_FAILOVER_IMAGE
 175                 ldscript /arch/i386/lib/failover_failover.lds
 176     end
 177 else
 178     if CONFIG_USE_FALLBACK_IMAGE
 179                 ldscript /arch/i386/lib/failover.lds
 180     end
 181 end
 182
 183 ##
 184 ## Setup RAM
 185 ##
 186         if CONFIG_USE_INIT
 187                 initobject cache_as_ram_auto.o
 188         else
 189                 mainboardinit ./cache_as_ram_auto.inc
 190         end
 191
 192 ##
 193 ## Include the secondary Configuration files
 194 ##
 195 config chip.h
 196
 197 chip northbridge/amd/amdk8/root_complex
 198         device apic_cluster 0 on
 199                 chip cpu/amd/socket_F
 200                         device apic 0 on end
 201                 end
 202         end
 203         device pci_domain 0 on
 204                 chip northbridge/amd/amdk8 #mc0
 205                         device pci 18.0 on
 206                                 #  devices on link 0, link 0 == LDT 0
 207                                 chip southbridge/nvidia/mcp55
 208                                         device pci 0.0 on end   # HT
 209                                         device pci 1.0 on # LPC
 210                                                 chip superio/winbond/w83627ehg
 211                                                         device pnp 2e.0 off #  Floppy
 212                                                                 io 0x60 = 0x3f0
 213                                                                 irq 0x70 = 6
 214                                                                 drq 0x74 = 2
 215                                                         end
 216                                                         device pnp 2e.1 off #  Parallel Port
 217                                                                 io 0x60 = 0x378
 218                                                                 irq 0x70 = 7
 219                                                         end
 220                                                         device pnp 2e.2 on #  Com1
 221                                                                 io 0x60 = 0x3f8
 222                                                                 irq 0x70 = 4
 223                                                         end
 224                                                         device pnp 2e.3 off #  Com2
 225                                                                 io 0x60 = 0x2f8
 226                                                                 irq 0x70 = 3
 227                                                         end
 228                                                         device pnp 2e.5 on #  Keyboard
 229                                                                 io 0x60 = 0x60
 230                                                                 io 0x62 = 0x64
 231                                                                 irq 0x70 = 1
 232                                                                 irq 0x72 = 12
 233                                                         end
 234                                                         device pnp 2e.6 off  # SFI
 235                                                                 io 0x62 = 0x100
 236                                                         end
 237                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 238                                                                 io 0x60 = 0x220
 239                                                                 io 0x62 = 0x300
 240                                                                 irq 0x70 = 9
 241                                                         end
 242                                                         device pnp 2e.8 off end #  WDTO_PLED
 243                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 244                                                         device pnp 2e.a off end #  ACPI
 245                                                         device pnp 2e.b on #  HW Monitor
 246                                                                 io 0x60 = 0x290
 247                                                                 irq 0x70 = 5
 248                                                         end
 249                                                 end
 250                                         end
 251                                         device pci 1.1 on # SM 0
 252                                                 chip drivers/generic/generic #dimm 0-0-0
 253                                                         device i2c 50 on end
 254                                                 end
 255                                                 chip drivers/generic/generic #dimm 0-0-1
 256                                                         device i2c 51 on end
 257                                                 end
 258                                                 chip drivers/generic/generic #dimm 0-1-0
 259                                                         device i2c 52 on end
 260                                                 end
 261                                                 chip drivers/generic/generic #dimm 0-1-1
 262                                                         device i2c 53 on end
 263                                                 end
 264                                                 chip drivers/generic/generic #dimm 1-0-0
 265                                                         device i2c 54 on end
 266                                                 end
 267                                                 chip drivers/generic/generic #dimm 1-0-1
 268                                                         device i2c 55 on end
 269                                                 end
 270                                                 chip drivers/generic/generic #dimm 1-1-0
 271                                                         device i2c 56 on end
 272                                                 end
 273                                                 chip drivers/generic/generic #dimm 1-1-1
 274                                                         device i2c 57 on end
 275                                                 end
 276                                         end # SM
 277                                         device pci 1.1 on # SM 1
 278 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 279 #                                               chip drivers/generic/generic #PCIXA Slot1
 280 #                                                       device i2c 50 on end
 281 #                                               end
 282 #                                               chip drivers/generic/generic #PCIXB Slot1
 283 #                                                       device i2c 51 on end
 284 #                                               end
 285 #                                               chip drivers/generic/generic #PCIXB Slot2
 286 #                                                       device i2c 52 on end
 287 #                                               end
 288 #                                               chip drivers/generic/generic #PCI Slot1
 289 #                                                       device i2c 53 on end
 290 #                                               end
 291 #                                               chip drivers/generic/generic #Master MCP55 PCI-E
 292 #                                                       device i2c 54 on end
 293 #                                               end
 294 #                                               chip drivers/generic/generic #Slave MCP55 PCI-E
 295 #                                                       device i2c 55 on end
 296 #                                               end
 297                                                 chip drivers/generic/generic #MAC EEPROM
 298                                                         device i2c 51 on end
 299                                                 end
 300
 301                                         end # SM
 302                                         device pci 2.0 on end # USB 1.1
 303                                         device pci 2.1 on end # USB 2
 304                                         device pci 4.0 on end # IDE
 305                                         device pci 5.0 on end # SATA 0
 306                                         device pci 5.1 on end # SATA 1
 307                                         device pci 5.2 on end # SATA 2
 308                                         device pci 6.0 on end # PCI
 309                                         device pci 6.1 on end # AZA
 310                                         device pci 8.0 on end # NIC
 311                                         device pci 9.0 on end # NIC
 312                                         device pci a.0 on end # PCI E 5
 313                                         device pci b.0 off end # PCI E 4
 314                                         device pci c.0 off end # PCI E 3
 315                                         device pci d.0 on end # PCI E 2
 316                                         device pci e.0 off end # PCI E 1
 317                                         device pci f.0 on end # PCI E 0
 318                                         register "ide0_enable" = "1"
 319                                         register "sata0_enable" = "1"
 320                                         register "sata1_enable" = "1"
 321                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 322                                         register "mac_eeprom_addr" = "0x51"
 323                                 end
 324                         end #  device pci 18.0
 325                         device pci 18.0 on end # Link 1
 326                         device pci 18.0 on
 327                                 #  devices on link 2, link 2 == LDT 2
 328                                 chip southbridge/nvidia/mcp55
 329                                         device pci 0.0 on end   # HT
 330                                         device pci 1.0 on end  # LPC
 331                                         device pci 1.1 on end # SM 0
 332                                         device pci 2.0 off end # USB 1.1
 333                                         device pci 2.1 off end # USB 2
 334                                         device pci 4.0 off end # IDE
 335                                         device pci 5.0 on end # SATA 0
 336                                         device pci 5.1 on end # SATA 1
 337                                         device pci 5.2 on end # SATA 2
 338                                         device pci 6.0 off end # PCI
 339                                         device pci 6.1 off end # AZA
 340                                         device pci 8.0 on end # NIC
 341                                         device pci 9.0 on end # NIC
 342                                         device pci a.0 on end # PCI E 5
 343                                         device pci b.0 off end # PCI E 4
 344                                         device pci c.0 off end # PCI E 3
 345                                         device pci d.0 on end # PCI E 2
 346                                         device pci e.0 on end # PCI E 1
 347                                         device pci f.0 on end # PCI E 0
 348                                         register "ide0_enable" = "1"
 349                                         register "sata0_enable" = "1"
 350                                         register "sata1_enable" = "1"
 351                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 352                                         register "mac_eeprom_addr" = "0x51"
 353                                 end
 354                         end # device pci 18.0
 355                         device pci 18.1 on end
 356                         device pci 18.2 on end
 357                         device pci 18.3 on end
 358                 end # mc0
 359
 360         end # PCI domain
 361
 362 #       chip drivers/generic/debug
 363 #               device pnp 0.0 off end # chip name
 364 #               device pnp 0.1 on end # pci_regs_all
 365 #               device pnp 0.2 on end # mem
 366 #               device pnp 0.3 off end # cpuid
 367 #               device pnp 0.4 on end # smbus_regs_all
 368 #               device pnp 0.5 off end # dual core msr
 369 #               device pnp 0.6 off end # cache size
 370 #               device pnp 0.7 off end # tsc
 371 #               device pnp 0.8 off  end # io
 372 #               device pnp 0.9 off end # io
 373 #       end
 374 end #root_complex