src/mainboard/nvidia/l1_2pvv/Config.lb

   1 ##
   2 ## This file is part of the LinuxBIOS project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The linuxBIOS bootloader.
  42 ##
  43 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of linuxBIOS will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83
  84 if HAVE_ACPI_TABLES
  85         object acpi_tables.o
  86         object fadt.o
  87         makerule dsdt.c
  88                 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
  89                 action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
  90                 action  "mv dsdt_lb.hex dsdt.c"
  91         end
  92         object ./dsdt.o
  93
  94         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  95
  96         if ACPI_SSDTX_NUM
  97             makerule ssdt6.c
  98                         depends "$(MAINBOARD)/dx/pci6.asl"
  99                         action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
 100                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
 101                         action  "mv pci6.hex ssdt6.c"
 102             end
 103             object ./ssdt6.o
 104             makerule ssdt5.c
 105                         depends "$(MAINBOARD)/dx/pci5.asl"
 106                         action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
 107                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
 108                         action  "mv pci5.hex ssdt5.c"
 109             end
 110             object ./ssdt5.o
 111         end
 112 end
 113
 114 if USE_DCACHE_RAM
 115
 116         if CONFIG_USE_INIT
 117                 makerule ./cache_as_ram_auto.o
 118                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 119                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 120                 end
 121         else
 122                 makerule ./cache_as_ram_auto.inc
 123                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 124                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 125                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 126                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 127                 end
 128         end
 129
 130 end
 131
 132 if USE_FAILOVER_IMAGE
 133 else
 134     if CONFIG_AP_CODE_IN_CAR
 135         makerule ./apc_auto.o
 136                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 137                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 138         end
 139         ldscript /arch/i386/init/ldscript_apc.lb
 140     end
 141 end
 142
 143
 144 ##
 145 ## Build our 16 bit and 32 bit linuxBIOS entry code
 146 ##
 147 if HAVE_FAILOVER_BOOT
 148     if USE_FAILOVER_IMAGE
 149         mainboardinit cpu/x86/16bit/entry16.inc
 150         ldscript /cpu/x86/16bit/entry16.lds
 151     end
 152 else
 153     if USE_FALLBACK_IMAGE
 154         mainboardinit cpu/x86/16bit/entry16.inc
 155         ldscript /cpu/x86/16bit/entry16.lds
 156     end
 157 end
 158
 159 mainboardinit cpu/x86/32bit/entry32.inc
 160
 161 if USE_DCACHE_RAM
 162         if CONFIG_USE_INIT
 163                 ldscript /cpu/x86/32bit/entry32.lds
 164         end
 165
 166         if CONFIG_USE_INIT
 167                 ldscript /cpu/amd/car/cache_as_ram.lds
 168         end
 169 end
 170
 171
 172 ##
 173 ## Build our reset vector (This is where linuxBIOS is entered)
 174 ##
 175 if HAVE_FAILOVER_BOOT
 176     if USE_FAILOVER_IMAGE
 177         mainboardinit cpu/x86/16bit/reset16.inc
 178         ldscript /cpu/x86/16bit/reset16.lds
 179     else
 180         mainboardinit cpu/x86/32bit/reset32.inc
 181         ldscript /cpu/x86/32bit/reset32.lds
 182     end
 183 else
 184     if USE_FALLBACK_IMAGE
 185         mainboardinit cpu/x86/16bit/reset16.inc
 186         ldscript /cpu/x86/16bit/reset16.lds
 187     else
 188         mainboardinit cpu/x86/32bit/reset32.inc
 189         ldscript /cpu/x86/32bit/reset32.lds
 190     end
 191 end
 192
 193 ##
 194 ## Include an id string (For safe flashing)
 195 ##
 196 mainboardinit southbridge/nvidia/mcp55/id.inc
 197 ldscript /southbridge/nvidia/mcp55/id.lds
 198
 199 ##
 200 ## ROMSTRAP table for MCP55
 201 ##
 202 if HAVE_FAILOVER_BOOT
 203     if USE_FAILOVER_IMAGE
 204         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 205         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 206     end
 207 else
 208     if USE_FALLBACK_IMAGE
 209         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 210         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 211     end
 212 end
 213
 214 if USE_DCACHE_RAM
 215         ##
 216         ## Setup Cache-As-Ram
 217         ##
 218         mainboardinit cpu/amd/car/cache_as_ram.inc
 219 end
 220
 221 ###
 222 ### This is the early phase of linuxBIOS startup
 223 ### Things are delicate and we test to see if we should
 224 ### failover to another image.
 225 ###
 226 if HAVE_FAILOVER_BOOT
 227     if USE_FAILOVER_IMAGE
 228         if USE_DCACHE_RAM
 229                 ldscript /arch/i386/lib/failover_failover.lds
 230         end
 231     end
 232 else
 233     if USE_FALLBACK_IMAGE
 234         if USE_DCACHE_RAM
 235                 ldscript /arch/i386/lib/failover.lds
 236         end
 237     end
 238 end
 239
 240 ##
 241 ## Setup RAM
 242 ##
 243 if USE_DCACHE_RAM
 244
 245         if CONFIG_USE_INIT
 246                 initobject cache_as_ram_auto.o
 247         else
 248                 mainboardinit ./cache_as_ram_auto.inc
 249         end
 250 end
 251
 252 ##
 253 ## Include the secondary Configuration files
 254 ##
 255 if CONFIG_CHIP_NAME
 256         config chip.h
 257 end
 258
 259 chip northbridge/amd/amdk8/root_complex
 260         device apic_cluster 0 on
 261                 chip cpu/amd/socket_F
 262                         device apic 0 on end
 263                 end
 264         end
 265         device pci_domain 0 on
 266                 chip northbridge/amd/amdk8 #mc0
 267                         device pci 18.0 on
 268                                 #  devices on link 0, link 0 == LDT 0
 269                                 chip southbridge/nvidia/mcp55
 270                                         device pci 0.0 on end   # HT
 271                                         device pci 1.0 on # LPC
 272                                                 chip superio/winbond/w83627ehg
 273                                                         device pnp 2e.0 off #  Floppy
 274                                                                 io 0x60 = 0x3f0
 275                                                                 irq 0x70 = 6
 276                                                                 drq 0x74 = 2
 277                                                         end
 278                                                         device pnp 2e.1 off #  Parallel Port
 279                                                                 io 0x60 = 0x378
 280                                                                 irq 0x70 = 7
 281                                                         end
 282                                                         device pnp 2e.2 on #  Com1
 283                                                                 io 0x60 = 0x3f8
 284                                                                 irq 0x70 = 4
 285                                                         end
 286                                                         device pnp 2e.3 off #  Com2
 287                                                                 io 0x60 = 0x2f8
 288                                                                 irq 0x70 = 3
 289                                                         end
 290                                                         device pnp 2e.5 on #  Keyboard
 291                                                                 io 0x60 = 0x60
 292                                                                 io 0x62 = 0x64
 293                                                                 irq 0x70 = 1
 294                                                                 irq 0x72 = 12
 295                                                         end
 296                                                         device pnp 2e.6 off  # SFI
 297                                                                 io 0x62 = 0x100
 298                                                         end
 299                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 300                                                                 io 0x60 = 0x220
 301                                                                 io 0x62 = 0x300
 302                                                                 irq 0x70 = 9
 303                                                         end
 304                                                         device pnp 2e.8 off end #  WDTO_PLED
 305                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 306                                                         device pnp 2e.a off end #  ACPI
 307                                                         device pnp 2e.b on #  HW Monitor
 308                                                                 io 0x60 = 0x290
 309                                                                 irq 0x70 = 5
 310                                                         end
 311                                                 end
 312                                         end
 313                                         device pci 1.1 on # SM 0
 314                                                 chip drivers/generic/generic #dimm 0-0-0
 315                                                         device i2c 50 on end
 316                                                 end
 317                                                 chip drivers/generic/generic #dimm 0-0-1
 318                                                         device i2c 51 on end
 319                                                 end
 320                                                 chip drivers/generic/generic #dimm 0-1-0
 321                                                         device i2c 52 on end
 322                                                 end
 323                                                 chip drivers/generic/generic #dimm 0-1-1
 324                                                         device i2c 53 on end
 325                                                 end
 326                                                 chip drivers/generic/generic #dimm 1-0-0
 327                                                         device i2c 54 on end
 328                                                 end
 329                                                 chip drivers/generic/generic #dimm 1-0-1
 330                                                         device i2c 55 on end
 331                                                 end
 332                                                 chip drivers/generic/generic #dimm 1-1-0
 333                                                         device i2c 56 on end
 334                                                 end
 335                                                 chip drivers/generic/generic #dimm 1-1-1
 336                                                         device i2c 57 on end
 337                                                 end
 338                                         end # SM
 339                                         device pci 1.1 on # SM 1
 340 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 341 #                                                chip drivers/generic/generic #PCIXA Slot1
 342 #                                                        device i2c 50 on end
 343 #                                                end
 344 #                                                chip drivers/generic/generic #PCIXB Slot1
 345 #                                                        device i2c 51 on end
 346 #                                                end
 347 #                                                chip drivers/generic/generic #PCIXB Slot2
 348 #                                                        device i2c 52 on end
 349 #                                                end
 350 #                                                chip drivers/generic/generic #PCI Slot1
 351 #                                                        device i2c 53 on end
 352 #                                                end
 353 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 354 #                                                        device i2c 54 on end
 355 #                                                end
 356 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 357 #                                                        device i2c 55 on end
 358 #                                                end
 359                                                 chip drivers/generic/generic #MAC EEPROM
 360                                                         device i2c 51 on end
 361                                                 end
 362
 363                                         end # SM
 364                                         device pci 2.0 on end # USB 1.1
 365                                         device pci 2.1 on end # USB 2
 366                                         device pci 4.0 on end # IDE
 367                                         device pci 5.0 on end # SATA 0
 368                                         device pci 5.1 on end # SATA 1
 369                                         device pci 5.2 on end # SATA 2
 370                                         device pci 6.0 on end # PCI
 371                                         device pci 6.1 on end # AZA
 372                                         device pci 8.0 on end # NIC
 373                                         device pci 9.0 on end # NIC
 374                                         device pci a.0 on end # PCI E 5
 375                                         device pci b.0 off end # PCI E 4
 376                                         device pci c.0 off end # PCI E 3
 377                                         device pci d.0 on end # PCI E 2
 378                                         device pci e.0 off end # PCI E 1
 379                                         device pci f.0 on end # PCI E 0
 380                                         register "ide0_enable" = "1"
 381                                         register "sata0_enable" = "1"
 382                                         register "sata1_enable" = "1"
 383                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 384                                         register "mac_eeprom_addr" = "0x51"
 385                                 end
 386                         end #  device pci 18.0
 387                         device pci 18.0 on end # Link 1
 388                         device pci 18.0 on
 389                                 #  devices on link 2, link 2 == LDT 2
 390                                 chip southbridge/nvidia/mcp55
 391                                         device pci 0.0 on end   # HT
 392                                         device pci 1.0 on end  # LPC
 393                                         device pci 1.1 on end # SM 0
 394                                         device pci 2.0 off end # USB 1.1
 395                                         device pci 2.1 off end # USB 2
 396                                         device pci 4.0 off end # IDE
 397                                         device pci 5.0 on end # SATA 0
 398                                         device pci 5.1 on end # SATA 1
 399                                         device pci 5.2 on end # SATA 2
 400                                         device pci 6.0 off end # PCI
 401                                         device pci 6.1 off end # AZA
 402                                         device pci 8.0 on end # NIC
 403                                         device pci 9.0 on end # NIC
 404                                         device pci a.0 on end # PCI E 5
 405                                         device pci b.0 off end # PCI E 4
 406                                         device pci c.0 off end # PCI E 3
 407                                         device pci d.0 on end # PCI E 2
 408                                         device pci e.0 on end # PCI E 1
 409                                         device pci f.0 on end # PCI E 0
 410                                         register "ide0_enable" = "1"
 411                                         register "sata0_enable" = "1"
 412                                         register "sata1_enable" = "1"
 413                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 414                                         register "mac_eeprom_addr" = "0x51"
 415                                 end
 416                         end # device pci 18.0
 417                         device pci 18.1 on end
 418                         device pci 18.2 on end
 419                         device pci 18.3 on end
 420                 end # mc0
 421
 422         end # PCI domain
 423
 424 #       chip drivers/generic/debug
 425 #               device pnp 0.0 off end # chip name
 426 #                device pnp 0.1 on end # pci_regs_all
 427 #                device pnp 0.2 on end # mem
 428 #                device pnp 0.3 off end # cpuid
 429 #                device pnp 0.4 on end # smbus_regs_all
 430 #                device pnp 0.5 off end # dual core msr
 431 #                device pnp 0.6 off end # cache size
 432 #               device pnp 0.7 off end # tsc
 433 #                device pnp 0.8 off  end # io
 434 #                device pnp 0.9 off end # io
 435 #       end
 436 end #root_complex