src/mainboard/nvidia/l1_2pvv/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/failovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 #needed by irq_tables and mptable and acpi_tables
  34 object get_bus_conf.o
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  38
  39 if CONFIG_GENERATE_ACPI_TABLES
  40         object acpi_tables.o
  41         object fadt.o
  42         makerule dsdt.c
  43                 depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
  44                 action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
  45                 action  "mv dsdt_lb.hex dsdt.c"
  46         end
  47         object ./dsdt.o
  48
  49         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  50
  51         if CONFIG_ACPI_SSDTX_NUM
  52             makerule ssdt6.c
  53                         depends "$(CONFIG_MAINBOARD)/dx/pci6.asl"
  54                         action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci6.asl"
  55                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
  56                         action  "mv pci6.hex ssdt6.c"
  57             end
  58             object ./ssdt6.o
  59             makerule ssdt5.c
  60                         depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
  61                         action  "/usr/sbin/iasl -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
  62                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
  63                         action  "mv pci5.hex ssdt5.c"
  64             end
  65             object ./ssdt5.o
  66         end
  67 end
  68
  69         if CONFIG_USE_INIT
  70                 makerule ./cache_as_ram_auto.o
  71                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  72                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  73                 end
  74         else
  75                 makerule ./cache_as_ram_auto.inc
  76                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  77                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  78                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  79                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  80                 end
  81         end
  82
  83 if CONFIG_USE_FAILOVER_IMAGE
  84 else
  85     if CONFIG_AP_CODE_IN_CAR
  86         makerule ./apc_auto.o
  87                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  88                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  89         end
  90         ldscript /arch/i386/init/ldscript_apc.lb
  91     end
  92 end
  93
  94
  95 ##
  96 ## Build our 16 bit and 32 bit coreboot entry code
  97 ##
  98 if CONFIG_HAVE_FAILOVER_BOOT
  99     if CONFIG_USE_FAILOVER_IMAGE
 100         mainboardinit cpu/x86/16bit/entry16.inc
 101         ldscript /cpu/x86/16bit/entry16.lds
 102     end
 103 else
 104     if CONFIG_USE_FALLBACK_IMAGE
 105         mainboardinit cpu/x86/16bit/entry16.inc
 106         ldscript /cpu/x86/16bit/entry16.lds
 107     end
 108 end
 109
 110 mainboardinit cpu/x86/32bit/entry32.inc
 111
 112         if CONFIG_USE_INIT
 113                 ldscript /cpu/x86/32bit/entry32.lds
 114         end
 115
 116         if CONFIG_USE_INIT
 117                 ldscript /cpu/amd/car/cache_as_ram.lds
 118         end
 119
 120 ##
 121 ## Build our reset vector (This is where coreboot is entered)
 122 ##
 123 if CONFIG_HAVE_FAILOVER_BOOT
 124     if CONFIG_USE_FAILOVER_IMAGE
 125         mainboardinit cpu/x86/16bit/reset16.inc
 126         ldscript /cpu/x86/16bit/reset16.lds
 127     else
 128         mainboardinit cpu/x86/32bit/reset32.inc
 129         ldscript /cpu/x86/32bit/reset32.lds
 130     end
 131 else
 132     if CONFIG_USE_FALLBACK_IMAGE
 133         mainboardinit cpu/x86/16bit/reset16.inc
 134         ldscript /cpu/x86/16bit/reset16.lds
 135     else
 136         mainboardinit cpu/x86/32bit/reset32.inc
 137         ldscript /cpu/x86/32bit/reset32.lds
 138     end
 139 end
 140
 141 ##
 142 ## Include an id string (For safe flashing)
 143 ##
 144 mainboardinit arch/i386/lib/id.inc
 145 ldscript /arch/i386/lib/id.lds
 146
 147 ##
 148 ## ROMSTRAP table for MCP55
 149 ##
 150 if CONFIG_HAVE_FAILOVER_BOOT
 151     if CONFIG_USE_FAILOVER_IMAGE
 152         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 153         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 154     end
 155 else
 156     if CONFIG_USE_FALLBACK_IMAGE
 157         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 158         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 159     end
 160 end
 161
 162         ##
 163         ## Setup Cache-As-Ram
 164         ##
 165         mainboardinit cpu/amd/car/cache_as_ram.inc
 166
 167 ###
 168 ### This is the early phase of coreboot startup
 169 ### Things are delicate and we test to see if we should
 170 ### failover to another image.
 171 ###
 172 if CONFIG_HAVE_FAILOVER_BOOT
 173     if CONFIG_USE_FAILOVER_IMAGE
 174                 ldscript /arch/i386/lib/failover_failover.lds
 175     end
 176 else
 177     if CONFIG_USE_FALLBACK_IMAGE
 178                 ldscript /arch/i386/lib/failover.lds
 179     end
 180 end
 181
 182 ##
 183 ## Setup RAM
 184 ##
 185         if CONFIG_USE_INIT
 186                 initobject cache_as_ram_auto.o
 187         else
 188                 mainboardinit ./cache_as_ram_auto.inc
 189         end
 190
 191 ##
 192 ## Include the secondary Configuration files
 193 ##
 194 config chip.h
 195
 196 chip northbridge/amd/amdk8/root_complex
 197         device apic_cluster 0 on
 198                 chip cpu/amd/socket_F
 199                         device apic 0 on end
 200                 end
 201         end
 202         device pci_domain 0 on
 203                 chip northbridge/amd/amdk8 #mc0
 204                         device pci 18.0 on
 205                                 #  devices on link 0, link 0 == LDT 0
 206                                 chip southbridge/nvidia/mcp55
 207                                         device pci 0.0 on end   # HT
 208                                         device pci 1.0 on # LPC
 209                                                 chip superio/winbond/w83627ehg
 210                                                         device pnp 2e.0 off #  Floppy
 211                                                                 io 0x60 = 0x3f0
 212                                                                 irq 0x70 = 6
 213                                                                 drq 0x74 = 2
 214                                                         end
 215                                                         device pnp 2e.1 off #  Parallel Port
 216                                                                 io 0x60 = 0x378
 217                                                                 irq 0x70 = 7
 218                                                         end
 219                                                         device pnp 2e.2 on #  Com1
 220                                                                 io 0x60 = 0x3f8
 221                                                                 irq 0x70 = 4
 222                                                         end
 223                                                         device pnp 2e.3 off #  Com2
 224                                                                 io 0x60 = 0x2f8
 225                                                                 irq 0x70 = 3
 226                                                         end
 227                                                         device pnp 2e.5 on #  Keyboard
 228                                                                 io 0x60 = 0x60
 229                                                                 io 0x62 = 0x64
 230                                                                 irq 0x70 = 1
 231                                                                 irq 0x72 = 12
 232                                                         end
 233                                                         device pnp 2e.6 off  # SFI
 234                                                                 io 0x62 = 0x100
 235                                                         end
 236                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 237                                                                 io 0x60 = 0x220
 238                                                                 io 0x62 = 0x300
 239                                                                 irq 0x70 = 9
 240                                                         end
 241                                                         device pnp 2e.8 off end #  WDTO_PLED
 242                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 243                                                         device pnp 2e.a off end #  ACPI
 244                                                         device pnp 2e.b on #  HW Monitor
 245                                                                 io 0x60 = 0x290
 246                                                                 irq 0x70 = 5
 247                                                         end
 248                                                 end
 249                                         end
 250                                         device pci 1.1 on # SM 0
 251                                                 chip drivers/generic/generic #dimm 0-0-0
 252                                                         device i2c 50 on end
 253                                                 end
 254                                                 chip drivers/generic/generic #dimm 0-0-1
 255                                                         device i2c 51 on end
 256                                                 end
 257                                                 chip drivers/generic/generic #dimm 0-1-0
 258                                                         device i2c 52 on end
 259                                                 end
 260                                                 chip drivers/generic/generic #dimm 0-1-1
 261                                                         device i2c 53 on end
 262                                                 end
 263                                                 chip drivers/generic/generic #dimm 1-0-0
 264                                                         device i2c 54 on end
 265                                                 end
 266                                                 chip drivers/generic/generic #dimm 1-0-1
 267                                                         device i2c 55 on end
 268                                                 end
 269                                                 chip drivers/generic/generic #dimm 1-1-0
 270                                                         device i2c 56 on end
 271                                                 end
 272                                                 chip drivers/generic/generic #dimm 1-1-1
 273                                                         device i2c 57 on end
 274                                                 end
 275                                         end # SM
 276                                         device pci 1.1 on # SM 1
 277 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 278 #                                               chip drivers/generic/generic #PCIXA Slot1
 279 #                                                       device i2c 50 on end
 280 #                                               end
 281 #                                               chip drivers/generic/generic #PCIXB Slot1
 282 #                                                       device i2c 51 on end
 283 #                                               end
 284 #                                               chip drivers/generic/generic #PCIXB Slot2
 285 #                                                       device i2c 52 on end
 286 #                                               end
 287 #                                               chip drivers/generic/generic #PCI Slot1
 288 #                                                       device i2c 53 on end
 289 #                                               end
 290 #                                               chip drivers/generic/generic #Master MCP55 PCI-E
 291 #                                                       device i2c 54 on end
 292 #                                               end
 293 #                                               chip drivers/generic/generic #Slave MCP55 PCI-E
 294 #                                                       device i2c 55 on end
 295 #                                               end
 296                                                 chip drivers/generic/generic #MAC EEPROM
 297                                                         device i2c 51 on end
 298                                                 end
 299
 300                                         end # SM
 301                                         device pci 2.0 on end # USB 1.1
 302                                         device pci 2.1 on end # USB 2
 303                                         device pci 4.0 on end # IDE
 304                                         device pci 5.0 on end # SATA 0
 305                                         device pci 5.1 on end # SATA 1
 306                                         device pci 5.2 on end # SATA 2
 307                                         device pci 6.0 on end # PCI
 308                                         device pci 6.1 on end # AZA
 309                                         device pci 8.0 on end # NIC
 310                                         device pci 9.0 on end # NIC
 311                                         device pci a.0 on end # PCI E 5
 312                                         device pci b.0 off end # PCI E 4
 313                                         device pci c.0 off end # PCI E 3
 314                                         device pci d.0 on end # PCI E 2
 315                                         device pci e.0 off end # PCI E 1
 316                                         device pci f.0 on end # PCI E 0
 317                                         register "ide0_enable" = "1"
 318                                         register "sata0_enable" = "1"
 319                                         register "sata1_enable" = "1"
 320                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 321                                         register "mac_eeprom_addr" = "0x51"
 322                                 end
 323                         end #  device pci 18.0
 324                         device pci 18.0 on end # Link 1
 325                         device pci 18.0 on
 326                                 #  devices on link 2, link 2 == LDT 2
 327                                 chip southbridge/nvidia/mcp55
 328                                         device pci 0.0 on end   # HT
 329                                         device pci 1.0 on end  # LPC
 330                                         device pci 1.1 on end # SM 0
 331                                         device pci 2.0 off end # USB 1.1
 332                                         device pci 2.1 off end # USB 2
 333                                         device pci 4.0 off end # IDE
 334                                         device pci 5.0 on end # SATA 0
 335                                         device pci 5.1 on end # SATA 1
 336                                         device pci 5.2 on end # SATA 2
 337                                         device pci 6.0 off end # PCI
 338                                         device pci 6.1 off end # AZA
 339                                         device pci 8.0 on end # NIC
 340                                         device pci 9.0 on end # NIC
 341                                         device pci a.0 on end # PCI E 5
 342                                         device pci b.0 off end # PCI E 4
 343                                         device pci c.0 off end # PCI E 3
 344                                         device pci d.0 on end # PCI E 2
 345                                         device pci e.0 on end # PCI E 1
 346                                         device pci f.0 on end # PCI E 0
 347                                         register "ide0_enable" = "1"
 348                                         register "sata0_enable" = "1"
 349                                         register "sata1_enable" = "1"
 350                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 351                                         register "mac_eeprom_addr" = "0x51"
 352                                 end
 353                         end # device pci 18.0
 354                         device pci 18.1 on end
 355                         device pci 18.2 on end
 356                         device pci 18.3 on end
 357                 end # mc0
 358
 359         end # PCI domain
 360
 361 #       chip drivers/generic/debug
 362 #               device pnp 0.0 off end # chip name
 363 #               device pnp 0.1 on end # pci_regs_all
 364 #               device pnp 0.2 on end # mem
 365 #               device pnp 0.3 off end # cpuid
 366 #               device pnp 0.4 on end # smbus_regs_all
 367 #               device pnp 0.5 off end # dual core msr
 368 #               device pnp 0.6 off end # cache size
 369 #               device pnp 0.7 off end # tsc
 370 #               device pnp 0.8 off  end # io
 371 #               device pnp 0.9 off end # io
 372 #       end
 373 end #root_complex