src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6
   7
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <device/pci_def.h>
  11 #include <arch/io.h>
  12 #include <device/pnp_def.h>
  13 #include <arch/romcc_io.h>
  14 #include <cpu/x86/lapic.h>
  15 #include "option_table.h"
  16 #include "pc80/mc146818rtc_early.c"
  17 #include "pc80/serial.c"
  18 #include "console/console.c"
  19 #include "lib/ramtest.c"
  20
  21 #include <cpu/amd/model_fxx_rev.h>
  22
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27 #include "lib/delay.c"
  28
  29 #include "cpu/x86/lapic/boot_cpu.c"
  30 #include "northbridge/amd/amdk8/reset_test.c"
  31 #include "northbridge/amd/amdk8/debug.c"
  32 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  33
  34 #include "cpu/x86/mtrr/earlymtrr.c"
  35 #include "cpu/x86/bist.h"
  36
  37 #include "northbridge/amd/amdk8/setup_resource_map.c"
  38
  39 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  40
  41 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  42
  43 static void memreset_setup(void)
  44 {
  45         if (is_cpu_pre_c0()) {
  46                 /* Set the memreset low */
  47                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  48                 /* Ensure the BIOS has control of the memory lines */
  49                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  50         }
  51         else {
  52                 /* Ensure the CPU has controll of the memory lines */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  54         }
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59         if (is_cpu_pre_c0()) {
  60                 udelay(800);
  61                 /* Set memreset_high */
  62                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  63                 udelay(90);
  64         }
  65 }
  66
  67 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  68 {
  69         /* nothing to do */
  70 }
  71
  72 static inline int spd_read_byte(unsigned device, unsigned address)
  73 {
  74         return smbus_read_byte(device, address);
  75 }
  76
  77 #define QRANK_DIMM_SUPPORT 1
  78
  79 #include "northbridge/amd/amdk8/raminit.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "lib/generic_sdram.c"
  82
  83  /* newisys khepri does not want the default */
  84 #include "resourcemap.c"
  85
  86 #if CONFIG_LOGICAL_CPUS==1
  87 #define SET_NB_CFG_54 1
  88 #endif
  89 #include "cpu/amd/dualcore/dualcore.c"
  90
  91
  92
  93 #include "cpu/amd/car/post_cache_as_ram.c"
  94
  95 #include "cpu/amd/model_fxx/init_cpus.c"
  96
  97 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  98 #include "northbridge/amd/amdk8/early_ht.c"
  99
 100 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 101 {
 102         static const uint16_t spd_addr [] = {
 103                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 104                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 105 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 106                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 107                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 108 #endif
 109         };
 110
 111         int needs_reset;
 112         unsigned bsp_apicid = 0;
 113
 114         struct mem_controller ctrl[8];
 115         unsigned nodes;
 116
 117         if (!cpu_init_detectedx && boot_cpu()) {
 118                 /* Nothing special needs to be done to find bus 0 */
 119                 /* Allow the HT devices to be found */
 120
 121                 enumerate_ht_chain();
 122
 123                 /* Setup the amd8111 */
 124                 amd8111_enable_rom();
 125         }
 126
 127         if (bist == 0) {
 128                 bsp_apicid = init_cpus(cpu_init_detectedx);
 129         }
 130
 131 //      post_code(0x32);
 132
 133         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 134         uart_init();
 135         console_init();
 136
 137 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 138
 139         /* Halt if there was a built in self test failure */
 140         report_bist_failure(bist);
 141
 142         setup_khepri_resource_map();
 143 #if 0
 144         dump_pci_device(PCI_DEV(0, 0x18, 0));
 145         dump_pci_device(PCI_DEV(0, 0x19, 0));
 146 #endif
 147
 148         needs_reset = setup_coherent_ht_domain();
 149
 150         wait_all_core0_started();
 151 #if CONFIG_LOGICAL_CPUS==1
 152         // It is said that we should start core1 after all core0 launched
 153         start_other_cores();
 154         wait_all_other_cores_started(bsp_apicid);
 155 #endif
 156
 157         needs_reset |= ht_setup_chains_x();
 158
 159         if (needs_reset) {
 160                 print_info("ht reset -\n");
 161                 soft_reset();
 162         }
 163
 164         allow_all_aps_stop(bsp_apicid);
 165
 166         nodes = get_nodes();
 167         //It's the time to set ctrl now;
 168         fill_mem_ctrl(nodes, ctrl, spd_addr);
 169
 170         enable_smbus();
 171
 172         memreset_setup();
 173         sdram_initialize(nodes, ctrl);
 174
 175 #if 0
 176         dump_pci_devices();
 177 #endif
 178
 179         post_cache_as_ram();
 180
 181 }
 182