src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16 #include <lib.h>
  17 #include <spd.h>
  18 #include <cpu/amd/model_fxx_rev.h>
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void memreset_setup(void)
  36 {
  37         if (is_cpu_pre_c0()) {
  38                 /* Set the memreset low. */
  39                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  40                 /* Ensure the BIOS has control of the memory lines. */
  41                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  42         } else {
  43                 /* Ensure the CPU has control of the memory lines. */
  44                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  45         }
  46 }
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl)
  49 {
  50         if (is_cpu_pre_c0()) {
  51                 udelay(800);
  52                 /* Set memreset high. */
  53                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  54                 udelay(90);
  55         }
  56 }
  57
  58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "northbridge/amd/amdk8/coherent_ht.c"
  67 #include "lib/generic_sdram.c"
  68 #include "resourcemap.c"
  69 #include "cpu/amd/dualcore/dualcore.c"
  70 #include "cpu/amd/car/post_cache_as_ram.c"
  71 #include "cpu/amd/model_fxx/init_cpus.c"
  72 #include "northbridge/amd/amdk8/early_ht.c"
  73
  74 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  75 {
  76         static const uint16_t spd_addr [] = {
  77                 DIMM0, DIMM2, 0, 0,
  78                 DIMM1, DIMM3, 0, 0,
  79 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  80                 DIMM4, DIMM6, 0, 0,
  81                 DIMM5, DIMM7, 0, 0,
  82 #endif
  83         };
  84
  85         int needs_reset;
  86         unsigned bsp_apicid = 0, nodes;
  87         struct mem_controller ctrl[8];
  88
  89         if (!cpu_init_detectedx && boot_cpu()) {
  90                 /* Nothing special needs to be done to find bus 0 */
  91                 /* Allow the HT devices to be found */
  92                 enumerate_ht_chain();
  93         }
  94
  95         if (bist == 0)
  96                 bsp_apicid = init_cpus(cpu_init_detectedx);
  97
  98         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  99         uart_init();
 100         console_init();
 101
 102 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 103
 104         /* Halt if there was a built in self test failure */
 105         report_bist_failure(bist);
 106
 107         setup_khepri_resource_map();
 108 #if 0
 109         dump_pci_device(PCI_DEV(0, 0x18, 0));
 110         dump_pci_device(PCI_DEV(0, 0x19, 0));
 111 #endif
 112
 113         needs_reset = setup_coherent_ht_domain();
 114
 115         wait_all_core0_started();
 116 #if CONFIG_LOGICAL_CPUS==1
 117         // It is said that we should start core1 after all core0 launched
 118         start_other_cores();
 119         wait_all_other_cores_started(bsp_apicid);
 120 #endif
 121
 122         needs_reset |= ht_setup_chains_x();
 123
 124         if (needs_reset) {
 125                 print_info("ht reset -\n");
 126                 soft_reset();
 127         }
 128
 129         allow_all_aps_stop(bsp_apicid);
 130
 131         nodes = get_nodes();
 132         //It's the time to set ctrl now;
 133         fill_mem_ctrl(nodes, ctrl, spd_addr);
 134
 135         enable_smbus();
 136
 137         memreset_setup();
 138         sdram_initialize(nodes, ctrl);
 139
 140 #if 0
 141         dump_pci_devices();
 142 #endif
 143
 144         post_cache_as_ram();
 145 }