src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16 #include <lib.h>
  17 #include <spd.h>
  18
  19 #include <cpu/amd/model_fxx_rev.h>
  20
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  23 #include "northbridge/amd/amdk8/raminit.h"
  24 #include "cpu/amd/model_fxx/apic_timer.c"
  25 #include "lib/delay.c"
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/x86/mtrr/earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  40
  41 static void memreset_setup(void)
  42 {
  43         if (is_cpu_pre_c0()) {
  44                 /* Set the memreset low */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  46                 /* Ensure the BIOS has control of the memory lines */
  47                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  48         }
  49         else {
  50                 /* Ensure the CPU has controll of the memory lines */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  52         }
  53 }
  54
  55 static void memreset(int controllers, const struct mem_controller *ctrl)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 udelay(800);
  59                 /* Set memreset_high */
  60                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  61                 udelay(90);
  62         }
  63 }
  64
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67         /* nothing to do */
  68 }
  69
  70 static inline int spd_read_byte(unsigned device, unsigned address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75
  76 #include "northbridge/amd/amdk8/raminit.c"
  77 #include "northbridge/amd/amdk8/coherent_ht.c"
  78 #include "lib/generic_sdram.c"
  79
  80  /* newisys khepri does not want the default */
  81 #include "resourcemap.c"
  82
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85
  86
  87 #include "cpu/amd/car/post_cache_as_ram.c"
  88
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90
  91 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const uint16_t spd_addr [] = {
  97                         DIMM0, DIMM2, 0, 0,
  98                         DIMM1, DIMM3, 0, 0,
  99 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 100                         DIMM4, DIMM6, 0, 0,
 101                         DIMM5, DIMM7, 0, 0,
 102 #endif
 103         };
 104
 105         int needs_reset;
 106         unsigned bsp_apicid = 0;
 107
 108         struct mem_controller ctrl[8];
 109         unsigned nodes;
 110
 111         if (!cpu_init_detectedx && boot_cpu()) {
 112                 /* Nothing special needs to be done to find bus 0 */
 113                 /* Allow the HT devices to be found */
 114
 115                 enumerate_ht_chain();
 116
 117                 /* Setup the amd8111 */
 118                 amd8111_enable_rom();
 119         }
 120
 121         if (bist == 0) {
 122                 bsp_apicid = init_cpus(cpu_init_detectedx);
 123         }
 124
 125 //      post_code(0x32);
 126
 127         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 128         uart_init();
 129         console_init();
 130
 131 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 132
 133         /* Halt if there was a built in self test failure */
 134         report_bist_failure(bist);
 135
 136         setup_khepri_resource_map();
 137 #if 0
 138         dump_pci_device(PCI_DEV(0, 0x18, 0));
 139         dump_pci_device(PCI_DEV(0, 0x19, 0));
 140 #endif
 141
 142         needs_reset = setup_coherent_ht_domain();
 143
 144         wait_all_core0_started();
 145 #if CONFIG_LOGICAL_CPUS==1
 146         // It is said that we should start core1 after all core0 launched
 147         start_other_cores();
 148         wait_all_other_cores_started(bsp_apicid);
 149 #endif
 150
 151         needs_reset |= ht_setup_chains_x();
 152
 153         if (needs_reset) {
 154                 print_info("ht reset -\n");
 155                 soft_reset();
 156         }
 157
 158         allow_all_aps_stop(bsp_apicid);
 159
 160         nodes = get_nodes();
 161         //It's the time to set ctrl now;
 162         fill_mem_ctrl(nodes, ctrl, spd_addr);
 163
 164         enable_smbus();
 165
 166         memreset_setup();
 167         sdram_initialize(nodes, ctrl);
 168
 169 #if 0
 170         dump_pci_devices();
 171 #endif
 172
 173         post_cache_as_ram();
 174
 175 }
 176