src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16 #include <lib.h>
  17 #include <spd.h>
  18 #include <cpu/amd/model_fxx_rev.h>
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void memreset_setup(void)
  36 {
  37         if (is_cpu_pre_c0()) {
  38                 /* Set the memreset low */
  39                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  40                 /* Ensure the BIOS has control of the memory lines */
  41                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  42         }
  43         else {
  44                 /* Ensure the CPU has controll of the memory lines */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  46         }
  47 }
  48
  49 static void memreset(int controllers, const struct mem_controller *ctrl)
  50 {
  51         if (is_cpu_pre_c0()) {
  52                 udelay(800);
  53                 /* Set memreset_high */
  54                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  55                 udelay(90);
  56         }
  57 }
  58
  59 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  60 {
  61         /* nothing to do */
  62 }
  63
  64 static inline int spd_read_byte(unsigned device, unsigned address)
  65 {
  66         return smbus_read_byte(device, address);
  67 }
  68
  69 #include "northbridge/amd/amdk8/raminit.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72 #include "resourcemap.c" /* newisys khepri does not want the default */
  73 #include "cpu/amd/dualcore/dualcore.c"
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  77 #include "northbridge/amd/amdk8/early_ht.c"
  78
  79 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  80 {
  81         static const uint16_t spd_addr [] = {
  82                         DIMM0, DIMM2, 0, 0,
  83                         DIMM1, DIMM3, 0, 0,
  84 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  85                         DIMM4, DIMM6, 0, 0,
  86                         DIMM5, DIMM7, 0, 0,
  87 #endif
  88         };
  89
  90         int needs_reset;
  91         unsigned bsp_apicid = 0;
  92
  93         struct mem_controller ctrl[8];
  94         unsigned nodes;
  95
  96         if (!cpu_init_detectedx && boot_cpu()) {
  97                 /* Nothing special needs to be done to find bus 0 */
  98                 /* Allow the HT devices to be found */
  99
 100                 enumerate_ht_chain();
 101
 102                 /* Setup the amd8111 */
 103                 amd8111_enable_rom();
 104         }
 105
 106         if (bist == 0) {
 107                 bsp_apicid = init_cpus(cpu_init_detectedx);
 108         }
 109
 110 //      post_code(0x32);
 111
 112         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 113         uart_init();
 114         console_init();
 115
 116 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         setup_khepri_resource_map();
 122 #if 0
 123         dump_pci_device(PCI_DEV(0, 0x18, 0));
 124         dump_pci_device(PCI_DEV(0, 0x19, 0));
 125 #endif
 126
 127         needs_reset = setup_coherent_ht_domain();
 128
 129         wait_all_core0_started();
 130 #if CONFIG_LOGICAL_CPUS==1
 131         // It is said that we should start core1 after all core0 launched
 132         start_other_cores();
 133         wait_all_other_cores_started(bsp_apicid);
 134 #endif
 135
 136         needs_reset |= ht_setup_chains_x();
 137
 138         if (needs_reset) {
 139                 print_info("ht reset -\n");
 140                 soft_reset();
 141         }
 142
 143         allow_all_aps_stop(bsp_apicid);
 144
 145         nodes = get_nodes();
 146         //It's the time to set ctrl now;
 147         fill_mem_ctrl(nodes, ctrl, spd_addr);
 148
 149         enable_smbus();
 150
 151         memreset_setup();
 152         sdram_initialize(nodes, ctrl);
 153
 154 #if 0
 155         dump_pci_devices();
 156 #endif
 157
 158         post_cache_as_ram();
 159 }