3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses HARD_RESET_FUNCTION
10 uses HAVE_OPTION_TABLE
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_STREAM
21 uses CONFIG_ROM_STREAM_START
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
35 uses LINUXBIOS_EXTRA_VERSION
40 uses DEFAULT_CONSOLE_LOGLEVEL
41 uses MAXIMUM_CONSOLE_LOGLEVEL
42 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
43 uses CONFIG_CONSOLE_SERIAL8250
54 ## ROM_SIZE is the size of boot ROM that this board will use.
56 default ROM_SIZE=524288
59 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
61 default FALLBACK_SIZE=131072
64 ## Build code for the fallback boot
66 default HAVE_FALLBACK_BOOT=1
69 ## Build code to reset the motherboard from linuxBIOS
71 default HAVE_HARD_RESET=1
74 ## Funky hard reset implementation
76 default HARD_RESET_BUS=1
77 default HARD_RESET_DEVICE=4
78 default HARD_RESET_FUNCTION=0
81 ## Build code to export a programmable irq routing table
83 default HAVE_PIRQ_TABLE=1
84 default IRQ_SLOT_COUNT=9
87 ## Build code to export an x86 MP table
88 ## Useful for specifying IRQ routing values
90 default HAVE_MP_TABLE=1
93 ## Build code to export a CMOS option table
95 default HAVE_OPTION_TABLE=1
98 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
100 default LB_CKS_RANGE_START=49
101 default LB_CKS_RANGE_END=122
102 default LB_CKS_LOC=123
105 ## Build code for SMP support
106 ## Only worry about 2 micro processors
109 default CONFIG_MAX_CPUS=2
112 ## Build code to setup a generic IOAPIC
114 default CONFIG_IOAPIC=1
117 ## Clean up the motherboard id strings
119 default MAINBOARD_PART_NUMBER="KHEPRI"
120 default MAINBOARD_VENDOR="NEWISYS"
123 ### LinuxBIOS layout values
126 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
127 default ROM_IMAGE_SIZE = 65536
130 ## Use a small 8K stack
132 default STACK_SIZE=0x2000
135 ## Use a small 16K heap
137 default HEAP_SIZE=0x4000
140 ## Only use the option table in a normal image
142 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
145 ## LinuxBIOS C code runs at this location in RAM
147 default _RAMBASE=0x00004000
150 ## Load the payload from the ROM
152 default CONFIG_ROM_STREAM = 1
155 ### Defaults of options that you may want to override in the target config file
159 ## The default compiler
161 default CC="$(CROSS_COMPILE)gcc -m32"
165 ## The Serial Console
168 # To Enable the Serial Console
169 default CONFIG_CONSOLE_SERIAL8250=1
171 ## Select the serial console baud rate
172 default TTYS0_BAUD=115200
173 #default TTYS0_BAUD=57600
174 #default TTYS0_BAUD=38400
175 #default TTYS0_BAUD=19200
176 #default TTYS0_BAUD=9600
177 #default TTYS0_BAUD=4800
178 #default TTYS0_BAUD=2400
179 #default TTYS0_BAUD=1200
181 # Select the serial console base port
182 default TTYS0_BASE=0x3f8
184 # Select the serial protocol
185 # This defaults to 8 data bits, 1 stop bit, and no parity
186 default TTYS0_LCS=0x3
189 ### Select the linuxBIOS loglevel
191 ## EMERG 1 system is unusable
192 ## ALERT 2 action must be taken immediately
193 ## CRIT 3 critical conditions
194 ## ERR 4 error conditions
195 ## WARNING 5 warning conditions
196 ## NOTICE 6 normal but significant condition
197 ## INFO 7 informational
198 ## DEBUG 8 debug-level messages
199 ## SPEW 9 Way too many details
201 ## Request this level of debugging output
202 default DEFAULT_CONSOLE_LOGLEVEL=8
203 ## At a maximum only compile in this level of debugging
204 default MAXIMUM_CONSOLE_LOGLEVEL=8
207 ## Select power on after power fail setting
208 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"