3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_STREAM
19 uses CONFIG_ROM_STREAM_START
27 uses LB_CKS_RANGE_START
30 uses MAINBOARD_PART_NUMBER
33 uses LINUXBIOS_EXTRA_VERSION
38 uses DEFAULT_CONSOLE_LOGLEVEL
39 uses MAXIMUM_CONSOLE_LOGLEVEL
40 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 uses CONFIG_CONSOLE_SERIAL8250
54 ## ROM_SIZE is the size of boot ROM that this board will use.
56 default ROM_SIZE=524288
59 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
61 default FALLBACK_SIZE=0x40000
64 ## Build code for the fallback boot
66 default HAVE_FALLBACK_BOOT=1
69 ## Build code to reset the motherboard from linuxBIOS
71 default HAVE_HARD_RESET=1
74 ## Build code to export a programmable irq routing table
76 default HAVE_PIRQ_TABLE=1
77 default IRQ_SLOT_COUNT=9
80 ## Build code to export an x86 MP table
81 ## Useful for specifying IRQ routing values
83 default HAVE_MP_TABLE=1
86 ## Build code to export a CMOS option table
88 default HAVE_OPTION_TABLE=1
91 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
93 default LB_CKS_RANGE_START=49
94 default LB_CKS_RANGE_END=122
95 default LB_CKS_LOC=123
98 ## Build code for SMP support
99 ## Only worry about 2 micro processors
102 default CONFIG_MAX_CPUS=2
103 default CONFIG_MAX_PHYSICAL_CPUS=2
106 ## Build code to setup a generic IOAPIC
108 default CONFIG_IOAPIC=1
111 ## Clean up the motherboard id strings
113 default MAINBOARD_PART_NUMBER="Khepri"
114 default MAINBOARD_VENDOR="Newisys"
117 ### LinuxBIOS layout values
120 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
121 default ROM_IMAGE_SIZE = 65536
124 ## Use a small 8K stack
126 default STACK_SIZE=0x2000
129 ## Use a small 16K heap
131 default HEAP_SIZE=0x4000
134 ## Only use the option table in a normal image
136 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
139 ## LinuxBIOS C code runs at this location in RAM
141 default _RAMBASE=0x00004000
144 ## Load the payload from the ROM
146 default CONFIG_ROM_STREAM = 1
149 ### Defaults of options that you may want to override in the target config file
153 ## The default compiler
155 default CC="$(CROSS_COMPILE)gcc -m32"
159 ## The Serial Console
162 # To Enable the Serial Console
163 default CONFIG_CONSOLE_SERIAL8250=1
165 ## Select the serial console baud rate
166 default TTYS0_BAUD=115200
167 #default TTYS0_BAUD=57600
168 #default TTYS0_BAUD=38400
169 #default TTYS0_BAUD=19200
170 #default TTYS0_BAUD=9600
171 #default TTYS0_BAUD=4800
172 #default TTYS0_BAUD=2400
173 #default TTYS0_BAUD=1200
175 # Select the serial console base port
176 default TTYS0_BASE=0x3f8
178 # Select the serial protocol
179 # This defaults to 8 data bits, 1 stop bit, and no parity
180 default TTYS0_LCS=0x3
183 ### Select the linuxBIOS loglevel
185 ## EMERG 1 system is unusable
186 ## ALERT 2 action must be taken immediately
187 ## CRIT 3 critical conditions
188 ## ERR 4 error conditions
189 ## WARNING 5 warning conditions
190 ## NOTICE 6 normal but significant condition
191 ## INFO 7 informational
192 ## DEBUG 8 debug-level messages
193 ## SPEW 9 Way too many details
195 ## Request this level of debugging output
196 default DEFAULT_CONSOLE_LOGLEVEL=8
197 ## At a maximum only compile in this level of debugging
198 default MAXIMUM_CONSOLE_LOGLEVEL=8
201 ## Select power on after power fail setting
202 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"