4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
37 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses HW_MEM_HOLE_SIZEK
62 uses CONFIG_USE_PRINTK_IN_CAR
69 ## ROM_SIZE is the size of boot ROM that this board will use.
71 default ROM_SIZE=524288
74 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
76 #default FALLBACK_SIZE=131072
78 default FALLBACK_SIZE=0x40000
81 ## Build code for the fallback boot
83 default HAVE_FALLBACK_BOOT=1
86 ## Build code to reset the motherboard from coreboot
88 default HAVE_HARD_RESET=1
91 ## Build code to export a programmable irq routing table
93 default HAVE_PIRQ_TABLE=1
94 default IRQ_SLOT_COUNT=15
97 ## Build code to export an x86 MP table
98 ## Useful for specifying IRQ routing values
100 default HAVE_MP_TABLE=1
103 ## Build code to export a CMOS option table
105 default HAVE_OPTION_TABLE=1
108 ## Move the default coreboot cmos range off of AMD RTC registers
110 default LB_CKS_RANGE_START=49
111 default LB_CKS_RANGE_END=122
112 default LB_CKS_LOC=123
115 ## Build code for SMP support
116 ## Only worry about 2 micro processors
119 default CONFIG_MAX_CPUS=4
120 default CONFIG_MAX_PHYSICAL_CPUS=2
121 default CONFIG_LOGICAL_CPUS=1
124 default HW_MEM_HOLE_SIZEK=0x100000
127 default CONFIG_CONSOLE_VGA=1
128 default CONFIG_PCI_ROM_RUN=1
132 ## enable CACHE_AS_RAM specifics
134 default USE_DCACHE_RAM=1
135 default DCACHE_RAM_BASE=0xcf000
136 default DCACHE_RAM_SIZE=0x1000
137 default CONFIG_USE_INIT=0
140 ## Build code to setup a generic IOAPIC
142 default CONFIG_IOAPIC=1
145 ## Clean up the motherboard id strings
147 default MAINBOARD_PART_NUMBER="Khepri"
148 default MAINBOARD_VENDOR="Newisys"
149 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
150 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
153 ### coreboot layout values
156 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
157 default ROM_IMAGE_SIZE = 65536
160 ## Use a small 8K stack
162 default STACK_SIZE=0x2000
165 ## Use a small 16K heap
167 default HEAP_SIZE=0x4000
170 ## Only use the option table in a normal image
172 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
175 ## Coreboot C code runs at this location in RAM
177 default _RAMBASE=0x00004000
180 ## Load the payload from the ROM
182 default CONFIG_ROM_PAYLOAD = 1
185 ### Defaults of options that you may want to override in the target config file
189 ## The default compiler
191 default CC="$(CROSS_COMPILE)gcc -m32"
195 ## Disable the gdb stub by default
197 default CONFIG_GDB_STUB=0
199 default CONFIG_USE_PRINTK_IN_CAR=1
202 ## The Serial Console
205 # To Enable the Serial Console
206 default CONFIG_CONSOLE_SERIAL8250=1
208 ## Select the serial console baud rate
209 default TTYS0_BAUD=115200
210 #default TTYS0_BAUD=57600
211 #default TTYS0_BAUD=38400
212 #default TTYS0_BAUD=19200
213 #default TTYS0_BAUD=9600
214 #default TTYS0_BAUD=4800
215 #default TTYS0_BAUD=2400
216 #default TTYS0_BAUD=1200
218 # Select the serial console base port
219 default TTYS0_BASE=0x3f8
221 # Select the serial protocol
222 # This defaults to 8 data bits, 1 stop bit, and no parity
223 default TTYS0_LCS=0x3
226 ### Select the coreboot loglevel
228 ## EMERG 1 system is unusable
229 ## ALERT 2 action must be taken immediately
230 ## CRIT 3 critical conditions
231 ## ERR 4 error conditions
232 ## WARNING 5 warning conditions
233 ## NOTICE 6 normal but significant condition
234 ## INFO 7 informational
235 ## DEBUG 8 debug-level messages
236 ## SPEW 9 Way too many details
238 ## Request this level of debugging output
239 default DEFAULT_CONSOLE_LOGLEVEL=8
240 ## At a maximum only compile in this level of debugging
241 default MAXIMUM_CONSOLE_LOGLEVEL=8
244 ## Select power on after power fail setting
245 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
252 default CONFIG_CBFS=0