1 ## XIP_ROM_SIZE must be a power of 2.
2 default XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
16 if HAVE_MP_TABLE object mptable.o end
17 if HAVE_PIRQ_TABLE object irq_tables.o end
23 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
24 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
30 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
31 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
32 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
33 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
39 ## Build our 16 bit and 32 bit coreboot entry code
42 mainboardinit cpu/x86/16bit/entry16.inc
43 ldscript /cpu/x86/16bit/entry16.lds
46 mainboardinit cpu/x86/32bit/entry32.inc
49 ldscript /cpu/x86/32bit/entry32.lds
53 ldscript /cpu/amd/car/cache_as_ram.lds
57 ## Build our reset vector (This is where coreboot is entered)
60 mainboardinit cpu/x86/16bit/reset16.inc
61 ldscript /cpu/x86/16bit/reset16.lds
63 mainboardinit cpu/x86/32bit/reset32.inc
64 ldscript /cpu/x86/32bit/reset32.lds
68 ## Include an id string (For safe flashing)
70 mainboardinit arch/i386/lib/id.inc
71 ldscript /arch/i386/lib/id.lds
76 mainboardinit cpu/amd/car/cache_as_ram.inc
79 ### This is the early phase of coreboot startup
80 ### Things are delicate and we test to see if we should
81 ### failover to another image.
84 ldscript /arch/i386/lib/failover.lds
88 ### O.k. We aren't just an intermediary anymore!
97 mainboardinit ./auto.inc
102 # FIXME: ROM for onboard VGA
104 chip northbridge/amd/amdk8/root_complex
105 device apic_cluster 0 on
106 chip cpu/amd/socket_940
109 chip cpu/amd/socket_940
114 device pci_domain 0 on
115 chip northbridge/amd/amdk8
116 device pci 18.0 on end # LDT 0
117 device pci 18.0 on # LDT 1
118 chip southbridge/amd/amd8131
119 device pci 0.0 on end
120 device pci 0.1 on end
121 device pci 1.0 on end
122 device pci 1.1 on end
124 chip southbridge/amd/amd8111
126 device pci 0.0 on end
127 device pci 0.1 on end
128 device pci 0.2 on end
129 device pci 1.0 on end
132 chip superio/winbond/w83627hf
133 device pnp 2e.0 on # Floppy
138 device pnp 2e.1 off # Parallel Port
142 device pnp 2e.2 on # Com1
146 device pnp 2e.3 on # Com2
150 device pnp 2e.5 on # Keyboard
156 device pnp 2e.6 off # CIR
159 device pnp 2e.7 off # GAME_MIDI_GIPO1
164 device pnp 2e.8 off end # GPIO2
165 device pnp 2e.9 off end # GPIO3
166 device pnp 2e.a off end # ACPI
167 device pnp 2e.b on # HW Monitor
173 device pci 1.1 on end
174 device pci 1.2 on end
175 device pci 1.3 on end
176 device pci 1.5 on end
177 device pci 1.6 on end
180 device pci 18.0 on end # LDT2
181 device pci 18.1 on end
182 device pci 18.2 on end
183 device pci 18.3 on end
185 chip northbridge/amd/amdk8
186 device pci 19.0 on end
187 device pci 19.0 on end
188 device pci 19.0 on end
189 device pci 19.1 on end
190 device pci 19.2 on end
191 device pci 19.3 on end