2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/pci.h>
28 #include <cpu/amd/amdfam10_sysconf.h>
30 #include "mb_sysconf.h"
34 static void *smp_write_config_table(void *v)
36 static const char sig[4] = "PCMP";
37 static const char oem[8] = "COREBOOT";
38 static const char productid[12] = "K9ND MS-9652";
39 struct mp_config_table *mc;
40 struct mb_sysconf_t *m;
45 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 memset(mc, 0, sizeof(*mc));
48 memcpy(mc->mpc_signature, sig, sizeof(sig));
49 mc->mpc_length = sizeof(*mc); /* initially just the header */
51 mc->mpc_checksum = 0; /* not yet computed */
52 memcpy(mc->mpc_oem, oem, sizeof(oem));
53 memcpy(mc->mpc_productid, productid, sizeof(productid));
56 mc->mpc_entry_count = 0; /* No entries yet... */
57 mc->mpc_lapic = LAPIC_ADDR;
62 smp_write_processors(mc);
69 /* define bus and isa numbers */
70 for(j= 0; j < 256 ; j++) {
72 smp_write_bus(mc, j, "PCI ");
74 smp_write_bus(mc, m->bus_isa, "ISA ");
76 /*I/O APICs: APIC ID Version State Address*/
82 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
84 res = find_resource(dev, PCI_BASE_ADDRESS_1);
86 smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
90 pci_write_config32(dev, 0x7c, dword);
93 pci_write_config32(dev, 0x80, dword);
96 pci_write_config32(dev, 0x84, dword);
103 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
120 for(j=7; j>=2; j--) {
121 if(!m->bus_mcp55[j]) continue;
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
132 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
133 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
134 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
135 /* There is no extension information... */
137 /* Compute the checksums */
138 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
139 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
140 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
141 mc, smp_next_mpe_entry(mc));
142 return smp_next_mpe_entry(mc);
145 unsigned long write_smp_table(unsigned long addr)
148 v = smp_write_floating_table(addr);
149 return (unsigned long)smp_write_config_table(v);