2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
27 #if CONFIG_LOGICAL_CPUS==1
28 #include <cpu/amd/quadcore.h>
31 #include <cpu/amd/amdfam10_sysconf.h>
34 #include "mb_sysconf.h"
36 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
37 struct mb_sysconf_t mb_sysconf;
39 /* Here you only need to set value in pci1234 for HT-IO that could be
40 installed or not You may need to preset pci1234 for HTIO board, please
41 refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
42 static u32 pci1234x[] = {
43 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
44 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
45 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
46 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
47 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
52 /* HT Chain device num, actually it is unit id base of every ht device
53 in chain, assume every chain only have 4 ht device at most */
55 static unsigned hcdnx[] = {
56 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
57 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
58 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
59 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
60 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
61 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
62 0x20202020, 0x20202020,
65 extern void get_pci1234(void);
67 static unsigned get_bus_conf_done = 0;
69 void get_bus_conf(void)
72 struct mb_sysconf_t *m;
77 printk(BIOS_SPEW, "get_bus_conf()\n");
79 if(get_bus_conf_done==1) return; //do it only once
81 get_bus_conf_done = 1;
83 sysconf.mb = &mb_sysconf;
86 memset(m, 0, sizeof(struct mb_sysconf_t));
88 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
89 for(i=0;i<sysconf.hc_possible_num; i++) {
90 sysconf.pci1234[i] = pci1234x[i];
91 sysconf.hcdn[i] = hcdnx[i];
96 m->bus_type[0] = 1; //pci
97 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
98 m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
101 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
103 m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
106 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
110 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
112 m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
115 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
119 for(i=0; i< sysconf.hc_possible_num; i++) {
120 if(!(sysconf.pci1234[i] & 0x1) ) continue;
122 unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
123 unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
124 for (j = busn; j <= busn_max; j++)
126 if(m->bus_isa <= busn_max)
127 m->bus_isa = busn_max + 1;
128 printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
131 /*I/O APICs: APIC ID Version State Address*/
132 #if CONFIG_LOGICAL_CPUS==1
133 apicid_base = get_apicid_base(1);
134 printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n");
136 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
137 printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n");
139 m->apicid_mcp55 = apicid_base+0;