2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 ## Copyright (C) 2010 Raptor Engineering
7 ## Written by Timothy Pearson <tpearson@raptorengineeringinc.com> for Raptor Engineering.
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 chip northbridge/amd/amdfam10/root_complex # Root complex
25 device lapic_cluster 0 on # (L)APIC cluster
26 chip cpu/amd/socket_F_1207 # CPU socket
27 device lapic 0 on end # Local APIC of the CPU
30 device pci_domain 0 on # PCI domain
31 chip northbridge/amd/amdfam10 # Northbridge / RAM controller
32 device pci 18.0 on # Link 0
33 chip southbridge/nvidia/mcp55 # Southbridge
34 device pci 0.0 on end # HT
35 device pci 1.0 on # LPC
36 chip superio/winbond/w83627ehg # Super I/O
37 device pnp 2e.0 on # Floppy
42 device pnp 2e.1 off # Parallel port
46 device pnp 2e.2 on # Com1
50 device pnp 2e.3 on # Com2
54 device pnp 2e.5 on # PS/2 keyboard & mouse
60 device pnp 2e.106 off # Serial flash interface (SFI)
63 device pnp 2e.007 off # GPIO 1
65 device pnp 2e.107 on # Game port
68 device pnp 2e.207 on # MIDI
72 device pnp 2e.307 off # GPIO 6
74 device pnp 2e.8 off # WDTO#, PLED
76 device pnp 2e.009 off # GPIO 2
78 device pnp 2e.109 off # GPIO 3
80 device pnp 2e.209 off # GPIO 4
82 device pnp 2e.309 off # GPIO 5
84 device pnp 2e.a off end # ACPI
85 device pnp 2e.b on # Hardware monitor
91 device pci 1.1 on # SM 0
92 chip drivers/generic/generic # DIMM 0-0-0
95 chip drivers/generic/generic # DIMM 0-0-1
98 chip drivers/generic/generic # DIMM 0-1-0
101 chip drivers/generic/generic # DIMM 0-1-1
104 chip drivers/generic/generic # DIMM 1-0-0
107 chip drivers/generic/generic # DIMM 1-0-1
110 chip drivers/generic/generic # DIMM 1-1-0
113 chip drivers/generic/generic # DIMM 1-1-1
117 device pci 1.1 on # SM 1
118 # PCI device SMBus address will
119 # depend on addon PCI device, do
120 # we need to scan_smbus_bus?
121 # chip drivers/generic/generic # PCIXA slot 1
122 # device i2c 50 on end
124 # chip drivers/generic/generic # PCIXB slot 1
125 # device i2c 51 on end
127 # chip drivers/generic/generic # PCIXB slot 2
128 # device i2c 52 on end
130 # chip drivers/generic/generic # PCI slot 1
131 # device i2c 53 on end
133 # chip drivers/generic/generic # Master MCP55 PCI-E
134 # device i2c 54 on end
136 # chip drivers/generic/generic # Slave MCP55 PCI-E
137 # device i2c 55 on end
139 # chip drivers/generic/generic # MAC EEPROM
140 # device i2c 51 on end
143 device pci 2.0 on end # USB 1.1
144 device pci 2.1 on end # USB 2
145 device pci 4.0 on end # IDE
146 device pci 5.0 on end # SATA 0
147 device pci 5.1 on end # SATA 1
148 device pci 5.2 on end # SATA 2
149 device pci 6.1 on end # AZA
150 device pci 8.0 on end # NIC
151 device pci 9.0 on end # NIC
152 register "ide0_enable" = "1"
153 register "sata0_enable" = "1"
154 register "sata1_enable" = "1"
155 # 1: SMBus under 2e.8, 2: SM0 3: SM1
156 register "mac_eeprom_smbus" = "3"
157 register "mac_eeprom_addr" = "0x51"
160 device pci 18.0 on end # HT 1.0
161 device pci 18.0 on end # HT 2.0
162 device pci 18.1 on end
163 device pci 18.2 on end
164 device pci 18.3 on end
165 device pci 18.4 on end
168 # chip drivers/generic/debug
169 # device pnp 0.0 off end # chip name
170 # device pnp 0.1 on end # pci_regs_all
171 # device pnp 0.2 on end # mem
172 # device pnp 0.3 off end # cpuid
173 # device pnp 0.4 on end # smbus_regs_all
174 # device pnp 0.5 off end # dual core msr
175 # device pnp 0.6 off end # cache size
176 # device pnp 0.7 off end # tsc
177 # device pnp 0.8 off end # io
178 # device pnp 0.9 off end # io