src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define RAMINIT_SYSINFO 1
  26 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  27
  28 #define SET_NB_CFG_54 1
  29
  30 //used by raminit
  31 #define QRANK_DIMM_SUPPORT 1
  32
  33 //used by init_cpus and fidvid
  34 #define SET_FIDVID 1
  35 //if we want to wait for core1 done before DQS training, set it to 0
  36 #define SET_FIDVID_CORE0_ONLY 1
  37
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <device/pci_def.h>
  41 #include <arch/io.h>
  42 #include <device/pnp_def.h>
  43 #include <arch/romcc_io.h>
  44 #include <cpu/x86/lapic.h>
  45 #include "option_table.h"
  46 #include "pc80/mc146818rtc_early.c"
  47 #include "pc80/serial.c"
  48 #include "console/console.c"
  49
  50 #include <cpu/amd/model_fxx_rev.h>
  51 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  52 #include "northbridge/amd/amdk8/raminit.h"
  53 #include "cpu/amd/model_fxx/apic_timer.c"
  54 #include "lib/delay.c"
  55
  56 #include "cpu/x86/lapic/boot_cpu.c"
  57 #include "northbridge/amd/amdk8/reset_test.c"
  58 #include "northbridge/amd/amdk8/debug.c"
  59 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  60
  61 #include "cpu/x86/mtrr/earlymtrr.c"
  62 #include "cpu/x86/bist.h"
  63
  64 #include "northbridge/amd/amdk8/setup_resource_map.c"
  65
  66 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  67 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  68
  69 #include <device/pci_ids.h>
  70 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  71 static void memreset_setup(void)
  72 {
  73 }
  74
  75 static void memreset(int controllers, const struct mem_controller *ctrl)
  76 {
  77 }
  78
  79 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  80 {
  81 #define SMBUS_SWITCH1 0x70
  82 #define SMBUS_SWITCH2 0x72
  83         unsigned device=(ctrl->channel0[0])>>8;
  84         smbus_send_byte(SMBUS_SWITCH1, device);
  85        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  86 }
  87
  88 #if 0
  89 static inline void change_i2c_mux(unsigned device)
  90 {
  91 #define SMBUS_SWITCH1 0x70
  92 #define SMBUS_SWITHC2 0x72
  93         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  94        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  95 }
  96 #endif
  97
  98 static inline int spd_read_byte(unsigned device, unsigned address)
  99 {
 100        return smbus_read_byte(device, address);
 101 }
 102
 103 //#define K8_4RANK_DIMM_SUPPORT 1
 104
 105 #include "northbridge/amd/amdk8/amdk8_f.h"
 106 #include "northbridge/amd/amdk8/raminit_f.c"
 107 #include "northbridge/amd/amdk8/coherent_ht.c"
 108 #include "northbridge/amd/amdk8/incoherent_ht.c"
 109 #include "lib/generic_sdram.c"
 110
 111  /* msi does not want the default */
 112 #include "resourcemap.c"
 113 #include "cpu/amd/dualcore/dualcore.c"
 114
 115 #define MCP55_NUM 1
 116 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 117 //set GPIO to input mode
 118 #define MCP55_MB_SETUP \
 119                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 120                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 121                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 122                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 123
 124 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 125
 126
 127
 128 #include "cpu/amd/car/post_cache_as_ram.c"
 129
 130 #include "cpu/amd/model_fxx/init_cpus.c"
 131 #include "cpu/amd/model_fxx/fidvid.c"
 132
 133 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 134 #include "northbridge/amd/amdk8/early_ht.c"
 135
 136 static void sio_setup(void)
 137 {
 138
 139         unsigned value;
 140         uint32_t dword;
 141         uint8_t byte;
 142
 143         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 144         byte |= 0x20;
 145         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 146
 147         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 148         dword |= (1<<0);
 149         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 150
 151 }
 152
 153 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 154 #define RC0 (2<<8)
 155 #define RC1 (1<<8)
 156
 157 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 158 {
 159        static const uint16_t spd_addr [] = {
 160                        RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 161                        RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 162 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 163                        RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 164                        RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 165 #endif
 166        };
 167
 168        unsigned bsp_apicid = 0;
 169         int needs_reset;
 170        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 171        char *p ;
 172
 173         if (!cpu_init_detectedx && boot_cpu()) {
 174                 /* Nothing special needs to be done to find bus 0 */
 175                 /* Allow the HT devices to be found */
 176
 177                 enumerate_ht_chain();
 178
 179                 sio_setup();
 180
 181                 /* Setup the mcp55 */
 182                 mcp55_enable_rom();
 183         }
 184
 185         if (bist == 0) {
 186                //init_cpus(cpu_init_detectedx);
 187                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 188         }
 189
 190        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 191         uart_init();
 192         console_init();
 193
 194        /* Halt if there was a built in self test failure */
 195        report_bist_failure(bist);
 196
 197         setup_ms9282_resource_map();
 198
 199        setup_coherent_ht_domain();
 200
 201         wait_all_core0_started();
 202
 203 #if CONFIG_LOGICAL_CPUS==1
 204         // It is said that we should start core1 after all core0 launched
 205         start_other_cores();
 206         //wait_all_other_cores_started(bsp_apicid);
 207 #endif
 208         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 209
 210        needs_reset = optimize_link_coherent_ht();
 211
 212        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 213
 214         needs_reset |= mcp55_early_setup_x();
 215
 216                if (needs_reset) {
 217                        print_info("ht reset -\n");
 218                        soft_reset();
 219                }
 220
 221         //It's the time to set ctrl now;
 222         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 223
 224        enable_smbus();
 225
 226 #if 0
 227         int i;
 228         for(i=4;i<8;i++) {
 229                 change_i2c_mux(i);
 230                 dump_smbus_registers();
 231         }
 232 #endif
 233
 234        memreset_setup();
 235
 236        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 237
 238        post_cache_as_ram();
 239
 240 }
 241