2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * Copyright (C) 2006 MSI
8 * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <device/pci_def.h>
29 #include <device/pnp_def.h>
30 #include <arch/romcc_io.h>
31 #include <cpu/x86/lapic.h>
32 #include <pc80/mc146818rtc.h>
33 #include <console/console.h>
35 #include <cpu/amd/model_fxx_rev.h>
36 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
37 #include "northbridge/amd/amdk8/raminit.h"
38 #include "cpu/amd/model_fxx/apic_timer.c"
39 #include "lib/delay.c"
41 #include "cpu/x86/lapic/boot_cpu.c"
42 #include "northbridge/amd/amdk8/reset_test.c"
43 #include "northbridge/amd/amdk8/debug.c"
44 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
46 #include "cpu/x86/mtrr/earlymtrr.c"
47 #include "cpu/x86/bist.h"
49 #include "northbridge/amd/amdk8/setup_resource_map.c"
51 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
52 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
54 #include <device/pci_ids.h>
55 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
57 static void memreset(int controllers, const struct mem_controller *ctrl)
61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
63 #define SMBUS_SWITCH1 0x70
64 #define SMBUS_SWITCH2 0x72
65 unsigned device=(ctrl->channel0[0])>>8;
66 smbus_send_byte(SMBUS_SWITCH1, device);
67 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
71 static inline void change_i2c_mux(unsigned device)
73 #define SMBUS_SWITCH1 0x70
74 #define SMBUS_SWITHC2 0x72
75 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
76 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
80 static inline int spd_read_byte(unsigned device, unsigned address)
82 return smbus_read_byte(device, address);
85 #include "northbridge/amd/amdk8/amdk8_f.h"
86 #include "northbridge/amd/amdk8/incoherent_ht.c"
87 #include "northbridge/amd/amdk8/coherent_ht.c"
88 #include "northbridge/amd/amdk8/raminit_f.c"
89 #include "lib/generic_sdram.c"
91 /* msi does not want the default */
92 #include "resourcemap.c"
93 #include "cpu/amd/dualcore/dualcore.c"
95 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
96 //set GPIO to input mode
97 #define MCP55_MB_SETUP \
98 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
99 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
100 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
101 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
103 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
105 #include "cpu/amd/car/post_cache_as_ram.c"
107 #include "cpu/amd/model_fxx/init_cpus.c"
108 // Disabled until it's actually used:
109 // #include "cpu/amd/model_fxx/fidvid.c"
111 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
112 #include "northbridge/amd/amdk8/early_ht.c"
114 static void sio_setup(void)
119 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
121 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
123 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
125 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
128 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
132 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
134 static const uint16_t spd_addr[] = {
136 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
137 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
139 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
140 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
143 unsigned bsp_apicid = 0;
145 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
146 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
148 if (!cpu_init_detectedx && boot_cpu()) {
149 /* Nothing special needs to be done to find bus 0 */
150 /* Allow the HT devices to be found */
152 enumerate_ht_chain();
156 /* Setup the mcp55 */
161 //init_cpus(cpu_init_detectedx);
162 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
165 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
169 /* Halt if there was a built in self test failure */
170 report_bist_failure(bist);
172 setup_ms9282_resource_map();
174 setup_coherent_ht_domain();
176 wait_all_core0_started();
178 #if CONFIG_LOGICAL_CPUS==1
179 // It is said that we should start core1 after all core0 launched
181 //wait_all_other_cores_started(bsp_apicid);
183 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
185 init_timer(); /* Need to use TMICT to synconize FID/VID. */
187 needs_reset = optimize_link_coherent_ht();
188 needs_reset |= optimize_link_incoherent_ht(sysinfo);
189 needs_reset |= mcp55_early_setup_x();
192 print_info("ht reset -\n");
196 //It's the time to set ctrl now;
197 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
205 dump_smbus_registers();
209 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);