src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define SET_NB_CFG_54 1
  26
  27 // used by init_cpus and fidvid (disabled until someone tests this)
  28 // #define SET_FIDVID 1
  29 #define SET_FIDVID 0
  30 // if we want to wait for core1 done before DQS training, set it to 0
  31 // #define SET_FIDVID_CORE0_ONLY 1
  32
  33 #include <stdint.h>
  34 #include <string.h>
  35 #include <device/pci_def.h>
  36 #include <arch/io.h>
  37 #include <device/pnp_def.h>
  38 #include <arch/romcc_io.h>
  39 #include <cpu/x86/lapic.h>
  40 #include <pc80/mc146818rtc.h>
  41 #include <console/console.h>
  42
  43 #include <cpu/amd/model_fxx_rev.h>
  44 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  45 #include "northbridge/amd/amdk8/raminit.h"
  46 #include "cpu/amd/model_fxx/apic_timer.c"
  47 #include "lib/delay.c"
  48
  49 #include "cpu/x86/lapic/boot_cpu.c"
  50 #include "northbridge/amd/amdk8/reset_test.c"
  51 #include "northbridge/amd/amdk8/debug.c"
  52 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  53
  54 #include "cpu/x86/mtrr/earlymtrr.c"
  55 #include "cpu/x86/bist.h"
  56
  57 #include "northbridge/amd/amdk8/setup_resource_map.c"
  58
  59 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  60 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  61
  62 #include <device/pci_ids.h>
  63 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71 #define SMBUS_SWITCH1 0x70
  72 #define SMBUS_SWITCH2 0x72
  73         unsigned device=(ctrl->channel0[0])>>8;
  74         smbus_send_byte(SMBUS_SWITCH1, device);
  75        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  76 }
  77
  78 #if 0
  79 static inline void change_i2c_mux(unsigned device)
  80 {
  81 #define SMBUS_SWITCH1 0x70
  82 #define SMBUS_SWITHC2 0x72
  83         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  84        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  85 }
  86 #endif
  87
  88 static inline int spd_read_byte(unsigned device, unsigned address)
  89 {
  90        return smbus_read_byte(device, address);
  91 }
  92
  93 #include "northbridge/amd/amdk8/amdk8_f.h"
  94 #include "northbridge/amd/amdk8/incoherent_ht.c"
  95 #include "northbridge/amd/amdk8/coherent_ht.c"
  96 #include "northbridge/amd/amdk8/raminit_f.c"
  97 #include "lib/generic_sdram.c"
  98
  99  /* msi does not want the default */
 100 #include "resourcemap.c"
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 104 //set GPIO to input mode
 105 #define MCP55_MB_SETUP \
 106                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 107                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 108                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 109                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 110
 111 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 112
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116 // Disabled until it's actually used:
 117 // #include "cpu/amd/model_fxx/fidvid.c"
 118
 119 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 static void sio_setup(void)
 123 {
 124         uint32_t dword;
 125         uint8_t byte;
 126
 127         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 128         byte |= 0x20;
 129         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 130
 131         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 132         dword |= (1<<0);
 133         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 134 }
 135
 136 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 137 #define RC0 (2<<8)
 138 #define RC1 (1<<8)
 139
 140 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 141 {
 142         static const uint16_t spd_addr[] = {
 143                 // Node 0
 144                 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 145                 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 146                 // node 1
 147                 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 148                 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 149         };
 150
 151         unsigned bsp_apicid = 0;
 152         int needs_reset;
 153         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 154                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 155
 156         if (!cpu_init_detectedx && boot_cpu()) {
 157                 /* Nothing special needs to be done to find bus 0 */
 158                 /* Allow the HT devices to be found */
 159
 160                 enumerate_ht_chain();
 161
 162                 sio_setup();
 163
 164                 /* Setup the mcp55 */
 165                 mcp55_enable_rom();
 166         }
 167
 168         if (bist == 0) {
 169                //init_cpus(cpu_init_detectedx);
 170                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 171         }
 172
 173         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 174         uart_init();
 175         console_init();
 176
 177         /* Halt if there was a built in self test failure */
 178         report_bist_failure(bist);
 179
 180         setup_ms9282_resource_map();
 181
 182         setup_coherent_ht_domain();
 183
 184         wait_all_core0_started();
 185
 186 #if CONFIG_LOGICAL_CPUS==1
 187         // It is said that we should start core1 after all core0 launched
 188         start_other_cores();
 189         //wait_all_other_cores_started(bsp_apicid);
 190 #endif
 191         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 192
 193         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 194
 195         needs_reset = optimize_link_coherent_ht();
 196         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 197         needs_reset |= mcp55_early_setup_x();
 198
 199         if (needs_reset) {
 200                 print_info("ht reset -\n");
 201                 soft_reset();
 202         }
 203
 204         //It's the time to set ctrl now;
 205         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 206
 207        enable_smbus();
 208
 209 #if 0
 210         int i;
 211         for(i=4;i<8;i++) {
 212                 change_i2c_mux(i);
 213                 dump_smbus_registers();
 214         }
 215 #endif
 216
 217        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 218
 219        post_cache_as_ram();
 220 }
 221