src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define SET_NB_CFG_54 1
  26
  27 //used by raminit
  28
  29 // used by init_cpus and fidvid (disabled until someone tests this)
  30 // #define SET_FIDVID 1
  31 #define SET_FIDVID 0
  32 // if we want to wait for core1 done before DQS training, set it to 0
  33 // #define SET_FIDVID_CORE0_ONLY 1
  34
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <device/pci_def.h>
  38 #include <arch/io.h>
  39 #include <device/pnp_def.h>
  40 #include <arch/romcc_io.h>
  41 #include <cpu/x86/lapic.h>
  42 #include <pc80/mc146818rtc.h>
  43 #include <console/console.h>
  44
  45 #include <cpu/amd/model_fxx_rev.h>
  46 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  47 #include "northbridge/amd/amdk8/raminit.h"
  48 #include "cpu/amd/model_fxx/apic_timer.c"
  49 #include "lib/delay.c"
  50
  51 #include "cpu/x86/lapic/boot_cpu.c"
  52 #include "northbridge/amd/amdk8/reset_test.c"
  53 #include "northbridge/amd/amdk8/debug.c"
  54 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  55
  56 #include "cpu/x86/mtrr/earlymtrr.c"
  57 #include "cpu/x86/bist.h"
  58
  59 #include "northbridge/amd/amdk8/setup_resource_map.c"
  60
  61 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  62 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  63
  64 #include <device/pci_ids.h>
  65 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69 }
  70
  71 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  72 {
  73 #define SMBUS_SWITCH1 0x70
  74 #define SMBUS_SWITCH2 0x72
  75         unsigned device=(ctrl->channel0[0])>>8;
  76         smbus_send_byte(SMBUS_SWITCH1, device);
  77        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  78 }
  79
  80 #if 0
  81 static inline void change_i2c_mux(unsigned device)
  82 {
  83 #define SMBUS_SWITCH1 0x70
  84 #define SMBUS_SWITHC2 0x72
  85         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  86        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  87 }
  88 #endif
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92        return smbus_read_byte(device, address);
  93 }
  94
  95 #include "northbridge/amd/amdk8/amdk8_f.h"
  96 #include "northbridge/amd/amdk8/incoherent_ht.c"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98 #include "northbridge/amd/amdk8/raminit_f.c"
  99 #include "lib/generic_sdram.c"
 100
 101  /* msi does not want the default */
 102 #include "resourcemap.c"
 103 #include "cpu/amd/dualcore/dualcore.c"
 104
 105 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 106 //set GPIO to input mode
 107 #define MCP55_MB_SETUP \
 108                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 109                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 110                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 111                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 112
 113 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 114
 115 #include "cpu/amd/car/post_cache_as_ram.c"
 116
 117 #include "cpu/amd/model_fxx/init_cpus.c"
 118 // Disabled until it's actually used:
 119 // #include "cpu/amd/model_fxx/fidvid.c"
 120
 121 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 122 #include "northbridge/amd/amdk8/early_ht.c"
 123
 124 static void sio_setup(void)
 125 {
 126         uint32_t dword;
 127         uint8_t byte;
 128
 129         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 130         byte |= 0x20;
 131         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 132
 133         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 134         dword |= (1<<0);
 135         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 136 }
 137
 138 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 139 #define RC0 (2<<8)
 140 #define RC1 (1<<8)
 141
 142 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 143 {
 144         static const uint16_t spd_addr[] = {
 145                 // Node 0
 146                 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 147                 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 148                 // node 1
 149                 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 150                 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 151         };
 152
 153         unsigned bsp_apicid = 0;
 154         int needs_reset;
 155         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 156                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 157
 158         if (!cpu_init_detectedx && boot_cpu()) {
 159                 /* Nothing special needs to be done to find bus 0 */
 160                 /* Allow the HT devices to be found */
 161
 162                 enumerate_ht_chain();
 163
 164                 sio_setup();
 165
 166                 /* Setup the mcp55 */
 167                 mcp55_enable_rom();
 168         }
 169
 170         if (bist == 0) {
 171                //init_cpus(cpu_init_detectedx);
 172                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 173         }
 174
 175         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 176         uart_init();
 177         console_init();
 178
 179         /* Halt if there was a built in self test failure */
 180         report_bist_failure(bist);
 181
 182         setup_ms9282_resource_map();
 183
 184         setup_coherent_ht_domain();
 185
 186         wait_all_core0_started();
 187
 188 #if CONFIG_LOGICAL_CPUS==1
 189         // It is said that we should start core1 after all core0 launched
 190         start_other_cores();
 191         //wait_all_other_cores_started(bsp_apicid);
 192 #endif
 193         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 194
 195         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 196
 197         needs_reset = optimize_link_coherent_ht();
 198         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 199         needs_reset |= mcp55_early_setup_x();
 200
 201         if (needs_reset) {
 202                 print_info("ht reset -\n");
 203                 soft_reset();
 204         }
 205
 206         //It's the time to set ctrl now;
 207         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 208
 209        enable_smbus();
 210
 211 #if 0
 212         int i;
 213         for(i=4;i<8;i++) {
 214                 change_i2c_mux(i);
 215                 dump_smbus_registers();
 216         }
 217 #endif
 218
 219        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 220
 221        post_cache_as_ram();
 222 }
 223