src/mainboard/msi/ms9282/resourcemap.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2006 MSI
  10  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  25  */
  26
  27 /*
  28  * MSI ms9282 needs a different resource map
  29  *
  30  */
  31
  32 static void setup_ms9282_resource_map(void)
  33 {
  34        static const unsigned int register_values[] = {
  35 #if 1
  36                /* Careful set limit registers before base registers which contain the enables */
  37                /* DRAM Limit i Registers
  38                 * F1:0x44 i = 0
  39                 * F1:0x4C i = 1
  40                 * F1:0x54 i = 2
  41                 * F1:0x5C i = 3
  42                 * F1:0x64 i = 4
  43                 * F1:0x6C i = 5
  44                 * F1:0x74 i = 6
  45                 * F1:0x7C i = 7
  46                 * [ 2: 0] Destination Node ID
  47                 *         000 = Node 0
  48                 *         001 = Node 1
  49                 *         010 = Node 2
  50                 *         011 = Node 3
  51                 *         100 = Node 4
  52                 *         101 = Node 5
  53                 *         110 = Node 6
  54                 *         111 = Node 7
  55                 * [ 7: 3] Reserved
  56                 * [10: 8] Interleave select
  57                 *         specifies the values of A[14:12] to use with interleave enable.
  58                 * [15:11] Reserved
  59                 * [31:16] DRAM Limit Address i Bits 39-24
  60                 *         This field defines the upper address bits of a 40 bit  address
  61                 *         that define the end of the DRAM region.
  62                 */
  63                PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  64                PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  65                PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  66                PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  67                PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  68                PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  69                PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  70                PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  71                /* DRAM Base i Registers
  72                 * F1:0x40 i = 0
  73                 * F1:0x48 i = 1
  74                 * F1:0x50 i = 2
  75                 * F1:0x58 i = 3
  76                 * F1:0x60 i = 4
  77                 * F1:0x68 i = 5
  78                 * F1:0x70 i = 6
  79                 * F1:0x78 i = 7
  80                 * [ 0: 0] Read Enable
  81                 *         0 = Reads Disabled
  82                 *         1 = Reads Enabled
  83                 * [ 1: 1] Write Enable
  84                 *         0 = Writes Disabled
  85                 *         1 = Writes Enabled
  86                 * [ 7: 2] Reserved
  87                 * [10: 8] Interleave Enable
  88                 *         000 = No interleave
  89                 *         001 = Interleave on A[12] (2 nodes)
  90                 *         010 = reserved
  91                 *         011 = Interleave on A[12] and A[14] (4 nodes)
  92                 *         100 = reserved
  93                 *         101 = reserved
  94                 *         110 = reserved
  95                 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  96                 * [15:11] Reserved
  97                 * [13:16] DRAM Base Address i Bits 39-24
  98                 *         This field defines the upper address bits of a 40-bit address
  99                 *         that define the start of the DRAM region.
 100                 */
 101                PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
 102                PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
 103                PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
 104                PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
 105                PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
 106                PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
 107                PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
 108                PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
 109 #endif
 110 #if 1
 111
 112                /* Memory-Mapped I/O Limit i Registers
 113                 * F1:0x84 i = 0
 114                 * F1:0x8C i = 1
 115                 * F1:0x94 i = 2
 116                 * F1:0x9C i = 3
 117                 * F1:0xA4 i = 4
 118                 * F1:0xAC i = 5
 119                 * F1:0xB4 i = 6
 120                 * F1:0xBC i = 7
 121                 * [ 2: 0] Destination Node ID
 122                 *         000 = Node 0
 123                 *         001 = Node 1
 124                 *         010 = Node 2
 125                 *         011 = Node 3
 126                 *         100 = Node 4
 127                 *         101 = Node 5
 128                 *         110 = Node 6
 129                 *         111 = Node 7
 130                 * [ 3: 3] Reserved
 131                 * [ 5: 4] Destination Link ID
 132                 *         00 = Link 0
 133                 *         01 = Link 1
 134                 *         10 = Link 2
 135                 *         11 = Reserved
 136                 * [ 6: 6] Reserved
 137                 * [ 7: 7] Non-Posted
 138                 *         0 = CPU writes may be posted
 139                 *         1 = CPU writes must be non-posted
 140                 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 141                 *         This field defines the upp adddress bits of a 40-bit address that
 142                 *         defines the end of a memory-mapped I/O region n
 143                 */
 144                PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 145                PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 146                PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 147                PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 148                PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 149                PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 150                PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 151 //             PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 152
 153                /* Memory-Mapped I/O Base i Registers
 154                 * F1:0x80 i = 0
 155                 * F1:0x88 i = 1
 156                 * F1:0x90 i = 2
 157                 * F1:0x98 i = 3
 158                 * F1:0xA0 i = 4
 159                 * F1:0xA8 i = 5
 160                 * F1:0xB0 i = 6
 161                 * F1:0xB8 i = 7
 162                 * [ 0: 0] Read Enable
 163                 *         0 = Reads disabled
 164                 *         1 = Reads Enabled
 165                 * [ 1: 1] Write Enable
 166                 *         0 = Writes disabled
 167                 *         1 = Writes Enabled
 168                 * [ 2: 2] Cpu Disable
 169                 *         0 = Cpu can use this I/O range
 170                 *         1 = Cpu requests do not use this I/O range
 171                 * [ 3: 3] Lock
 172                 *         0 = base/limit registers i are read/write
 173                 *         1 = base/limit registers i are read-only
 174                 * [ 7: 4] Reserved
 175                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 176                 *         This field defines the upper address bits of a 40bit address
 177                 *         that defines the start of memory-mapped I/O region i
 178                 */
 179                PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 180                PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 181                PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 182                PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 183                PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 184                PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 185                PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 186 //             PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 187 #endif
 188 #if 1
 189
 190                /* PCI I/O Limit i Registers
 191                 * F1:0xC4 i = 0
 192                 * F1:0xCC i = 1
 193                 * F1:0xD4 i = 2
 194                 * F1:0xDC i = 3
 195                 * [ 2: 0] Destination Node ID
 196                 *         000 = Node 0
 197                 *         001 = Node 1
 198                 *         010 = Node 2
 199                 *         011 = Node 3
 200                 *         100 = Node 4
 201                 *         101 = Node 5
 202                 *         110 = Node 6
 203                 *         111 = Node 7
 204                 * [ 3: 3] Reserved
 205                 * [ 5: 4] Destination Link ID
 206                 *         00 = Link 0
 207                 *         01 = Link 1
 208                 *         10 = Link 2
 209                 *         11 = reserved
 210                 * [11: 6] Reserved
 211                 * [24:12] PCI I/O Limit Address i
 212                 *         This field defines the end of PCI I/O region n
 213                 * [31:25] Reserved
 214                 */
 215                PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 216                PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 217                PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 218                PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 219
 220                /* PCI I/O Base i Registers
 221                 * F1:0xC0 i = 0
 222                 * F1:0xC8 i = 1
 223                 * F1:0xD0 i = 2
 224                 * F1:0xD8 i = 3
 225                 * [ 0: 0] Read Enable
 226                 *         0 = Reads Disabled
 227                 *         1 = Reads Enabled
 228                 * [ 1: 1] Write Enable
 229                 *         0 = Writes Disabled
 230                 *         1 = Writes Enabled
 231                 * [ 3: 2] Reserved
 232                 * [ 4: 4] VGA Enable
 233                 *         0 = VGA matches Disabled
 234                 *         1 = matches all address < 64K and where A[9:0] is in the
 235                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 236                 * [ 5: 5] ISA Enable
 237                 *         0 = ISA matches Disabled
 238                 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 239                 *             from matching agains this base/limit pair
 240                 * [11: 6] Reserved
 241                 * [24:12] PCI I/O Base i
 242                 *         This field defines the start of PCI I/O region n
 243                 * [31:25] Reserved
 244                 */
 245                PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
 246                PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 247                PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 248                PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 249 #endif
 250                /* Config Base and Limit i Registers
 251                 * F1:0xE0 i = 0
 252                 * F1:0xE4 i = 1
 253                 * F1:0xE8 i = 2
 254                 * F1:0xEC i = 3
 255                 * [ 0: 0] Read Enable
 256                 *         0 = Reads Disabled
 257                 *         1 = Reads Enabled
 258                 * [ 1: 1] Write Enable
 259                 *         0 = Writes Disabled
 260                 *         1 = Writes Enabled
 261                 * [ 2: 2] Device Number Compare Enable
 262                 *         0 = The ranges are based on bus number
 263                 *         1 = The ranges are ranges of devices on bus 0
 264                 * [ 3: 3] Reserved
 265                 * [ 6: 4] Destination Node
 266                 *         000 = Node 0
 267                 *         001 = Node 1
 268                 *         010 = Node 2
 269                 *         011 = Node 3
 270                 *         100 = Node 4
 271                 *         101 = Node 5
 272                 *         110 = Node 6
 273                 *         111 = Node 7
 274                 * [ 7: 7] Reserved
 275                 * [ 9: 8] Destination Link
 276                 *         00 = Link 0
 277                 *         01 = Link 1
 278                 *         10 = Link 2
 279                 *         11 - Reserved
 280                 * [15:10] Reserved
 281                 * [23:16] Bus Number Base i
 282                 *         This field defines the lowest bus number in configuration region i
 283                 * [31:24] Bus Number Limit i
 284                 *         This field defines the highest bus number in configuration region i
 285                 */
 286 #if 1
 287 //             PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
 288 //             PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
 289                PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 290                PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 291 #endif
 292
 293        };
 294
 295        int max;
 296        max = sizeof(register_values)/sizeof(register_values[0]);
 297        setup_resource_map(register_values, max);
 298 }
 299