src/mainboard/msi/ms9282/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define ASSEMBLY 1
  26 #define __ROMCC__
  27
  28 #define RAMINIT_SYSINFO 1
  29 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  30
  31 #define SET_NB_CFG_54 1
  32
  33 //used by raminit
  34 #define QRANK_DIMM_SUPPORT 1
  35
  36 //used by init_cpus and fidvid
  37 #define K8_SET_FIDVID 1
  38 //if we want to wait for core1 done before DQS training, set it to 0
  39 #define K8_SET_FIDVID_CORE0_ONLY 1
  40
  41 #define DEBUG_SMBUS 1
  42
  43 #include <stdint.h>
  44 #include <device/pci_def.h>
  45 #include <arch/io.h>
  46 #include <device/pnp_def.h>
  47 #include <arch/romcc_io.h>
  48 #include <cpu/x86/lapic.h>
  49 #include "option_table.h"
  50 #include "pc80/mc146818rtc_early.c"
  51 #include "pc80/serial.c"
  52 #include "arch/i386/lib/console.c"
  53
  54 #include <cpu/amd/model_fxx_rev.h>
  55 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  56 #include "northbridge/amd/amdk8/raminit.h"
  57 #include "cpu/amd/model_fxx/apic_timer.c"
  58 #include "lib/delay.c"
  59
  60 #if CONFIG_USE_INIT == 0
  61        #include "lib/memcpy.c"
  62 #endif
  63
  64 #include "cpu/x86/lapic/boot_cpu.c"
  65 #include "northbridge/amd/amdk8/reset_test.c"
  66 #include "northbridge/amd/amdk8/debug.c"
  67 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  68
  69 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  70 #include "cpu/x86/bist.h"
  71
  72 #include "northbridge/amd/amdk8/setup_resource_map.c"
  73
  74 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  75 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  76
  77 #include <device/pci_ids.h>
  78 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  79 static void memreset_setup(void)
  80 {
  81 }
  82
  83 static void memreset(int controllers, const struct mem_controller *ctrl)
  84 {
  85 }
  86
  87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  88 {
  89 #define SMBUS_SWITCH1 0x70
  90 #define SMBUS_SWITCH2 0x72
  91         unsigned device=(ctrl->channel0[0])>>8;
  92         smbus_send_byte(SMBUS_SWITCH1, device);
  93        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  94 }
  95
  96 #if 0
  97 static inline void change_i2c_mux(unsigned device)
  98 {
  99 #define SMBUS_SWITCH1 0x70
 100 #define SMBUS_SWITHC2 0x72
 101         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 102        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
 103 }
 104 #endif
 105
 106 static inline int spd_read_byte(unsigned device, unsigned address)
 107 {
 108        return smbus_read_byte(device, address);
 109 }
 110
 111 //#define K8_4RANK_DIMM_SUPPORT 1
 112
 113 #include "northbridge/amd/amdk8/amdk8_f.h"
 114 #include "northbridge/amd/amdk8/raminit_f.c"
 115 #include "northbridge/amd/amdk8/coherent_ht.c"
 116 #include "northbridge/amd/amdk8/incoherent_ht.c"
 117 #include "sdram/generic_sdram.c"
 118
 119  /* msi does not want the default */
 120 #include "resourcemap.c"
 121 #include "cpu/amd/dualcore/dualcore.c"
 122
 123 #define MCP55_NUM 1
 124 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 125 //set GPIO to input mode
 126 #define MCP55_MB_SETUP \
 127                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 128                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 129                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 130                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 131
 132 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 133
 134 #include "cpu/amd/car/copy_and_run.c"
 135
 136 #include "cpu/amd/car/post_cache_as_ram.c"
 137
 138 #include "cpu/amd/model_fxx/init_cpus.c"
 139 #include "cpu/amd/model_fxx/fidvid.c"
 140
 141 #if USE_FALLBACK_IMAGE == 1
 142
 143 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 144 #include "northbridge/amd/amdk8/early_ht.c"
 145
 146
 147 static void sio_setup(void)
 148 {
 149
 150         unsigned value;
 151         uint32_t dword;
 152         uint8_t byte;
 153
 154         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 155         byte |= 0x20;
 156         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 157
 158         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 159         dword |= (1<<0);
 160         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 161
 162
 163 }
 164 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 165 {
 166         unsigned last_boot_normal_x = last_boot_normal();
 167
 168         /* Is this a cpu only reset? or Is this a secondary cpu? */
 169         if ((cpu_init_detectedx) || (!boot_cpu())) {
 170                 if (last_boot_normal_x) {
 171                         goto normal_image;
 172                 } else {
 173                         goto fallback_image;
 174                 }
 175         }
 176
 177         /* Nothing special needs to be done to find bus 0 */
 178         /* Allow the HT devices to be found */
 179
 180         enumerate_ht_chain();
 181
 182         sio_setup();
 183
 184         /* Setup the mcp55 */
 185         mcp55_enable_rom();
 186
 187         /* Is this a deliberate reset by the bios */
 188         if (bios_reset_detected() && last_boot_normal_x) {
 189                 goto normal_image;
 190         }
 191         /* This is the primary cpu how should I boot? */
 192         else if (do_normal_boot()) {
 193                 goto normal_image;
 194         }
 195         else {
 196                 goto fallback_image;
 197         }
 198  normal_image:
 199         __asm__ volatile ("jmp __normal_image"
 200                 : /* outputs */
 201                 : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 202                 );
 203
 204  fallback_image:
 205        ;
 206 }
 207 #endif
 208
 209 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 210
 211 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 212 {
 213
 214 #if USE_FALLBACK_IMAGE == 1
 215         failover_process(bist, cpu_init_detectedx);
 216 #endif
 217         real_main(bist, cpu_init_detectedx);
 218
 219 }
 220
 221 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 222 #define RC0 (2<<8)
 223 #define RC1 (1<<8)
 224
 225 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 226 {
 227        static const uint16_t spd_addr [] = {
 228                        RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 229                        RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 230 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 231                        RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 232                        RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 233 #endif
 234        };
 235
 236        unsigned bsp_apicid = 0;
 237         int needs_reset;
 238        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 239        char *p ;
 240
 241         if (bist == 0) {
 242                //init_cpus(cpu_init_detectedx);
 243                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 244         }
 245
 246        w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
 247         uart_init();
 248         console_init();
 249
 250        /* Halt if there was a built in self test failure */
 251        report_bist_failure(bist);
 252
 253         setup_ms9282_resource_map();
 254
 255        setup_coherent_ht_domain();
 256
 257         wait_all_core0_started();
 258
 259 #if CONFIG_LOGICAL_CPUS==1
 260         // It is said that we should start core1 after all core0 launched
 261         start_other_cores();
 262         //wait_all_other_cores_started(bsp_apicid);
 263 #endif
 264         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 265
 266        needs_reset = optimize_link_coherent_ht();
 267
 268        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 269
 270         needs_reset |= mcp55_early_setup_x();
 271
 272                if (needs_reset) {
 273                        print_info("ht reset -\r\n");
 274                        soft_reset();
 275                }
 276
 277         //It's the time to set ctrl now;
 278         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 279
 280        enable_smbus();
 281
 282 #if 0
 283         int i;
 284         for(i=4;i<8;i++) {
 285                 change_i2c_mux(i);
 286                 dump_smbus_registers();
 287         }
 288 #endif
 289
 290        memreset_setup();
 291
 292        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 293
 294        post_cache_as_ram();
 295
 296 }