2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 uses USE_FALLBACK_IMAGE
29 uses HAVE_FALLBACK_BOOT
32 uses HAVE_OPTION_TABLE
34 uses CONFIG_MAX_PHYSICAL_CPUS
35 uses CONFIG_LOGICAL_CPUS
43 uses ROM_SECTION_OFFSET
44 uses CONFIG_ROM_PAYLOAD
45 uses CONFIG_ROM_PAYLOAD_START
53 uses LB_CKS_RANGE_START
57 uses MAINBOARD_PART_NUMBER
59 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
60 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
61 uses COREBOOT_EXTRA_VERSION
71 uses DEFAULT_CONSOLE_LOGLEVEL
72 uses MAXIMUM_CONSOLE_LOGLEVEL
73 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 uses CONFIG_CONSOLE_SERIAL8250
77 uses CONFIG_CONSOLE_VGA
78 uses CONFIG_PCI_ROM_RUN
79 #bx_b001- uses K8_HW_MEM_HOLE_SIZEK
80 uses K8_HT_FREQ_1G_SUPPORT
85 uses DCACHE_RAM_GLOBAL_VAR_SIZE
88 uses ENABLE_APIC_EXT_ID
92 uses HT_CHAIN_UNITID_BASE
93 uses HT_CHAIN_END_UNITID_BASE
94 #bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
95 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
97 uses SB_HT_CHAIN_ON_BUS0
100 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
101 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
102 uses CONFIG_PRECOMPRESSED_PAYLOAD
103 uses CONFIG_USE_PRINTK_IN_CAR
\r
105 ## ROM_SIZE is the size of boot ROM that this board will use.
107 default ROM_SIZE=524288
110 #bx- default ROM_SIZE=1048576
113 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
115 #default FALLBACK_SIZE=131072
117 default FALLBACK_SIZE=0x40000
124 ## Build code for the fallback boot
126 default HAVE_FALLBACK_BOOT=1
129 ## Build code to reset the motherboard from coreboot
131 default HAVE_HARD_RESET=1
134 ## Build code to export a programmable irq routing table
136 default HAVE_PIRQ_TABLE=1
137 default IRQ_SLOT_COUNT=11
140 ## Build code to export an x86 MP table
141 ## Useful for specifying IRQ routing values
143 default HAVE_MP_TABLE=1
146 ## Build code to export a CMOS option table
148 default HAVE_OPTION_TABLE=1
151 ## Move the default coreboot cmos range off of AMD RTC registers
153 default LB_CKS_RANGE_START=49
154 default LB_CKS_RANGE_END=122
155 default LB_CKS_LOC=123
158 ## Build code for SMP support
159 ## Only worry about 2 micro processors
162 default CONFIG_MAX_CPUS=4
163 default CONFIG_MAX_PHYSICAL_CPUS=2
164 default CONFIG_LOGICAL_CPUS=1
167 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
169 #Opteron K8 1G HT Support
170 default K8_HT_FREQ_1G_SUPPORT=1
172 ##HT Unit ID offset, default is 1, the typical one
173 default HT_CHAIN_UNITID_BASE=0x0
175 ##real SB Unit ID, default is 0x20, mean dont touch it at last
176 #default HT_CHAIN_END_UNITID_BASE=0x0
178 #make the SB HT chain on bus 0, default is not (0)
179 #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
181 ##bx_b005+ make the SB HT chain on bus 0
182 default SB_HT_CHAIN_ON_BUS0=1
184 ##only offset for SB chain?, default is yes(1)
185 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
188 default CONFIG_CONSOLE_VGA=1
189 default CONFIG_PCI_ROM_RUN=1
192 ## enable CACHE_AS_RAM specifics
194 default USE_DCACHE_RAM=1
195 default DCACHE_RAM_BASE=0xcc000
196 default DCACHE_RAM_SIZE=0x4000
197 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
198 default CONFIG_USE_INIT=0
200 default ENABLE_APIC_EXT_ID=1
201 default APIC_ID_OFFSET=0x10
202 default LIFT_BSP_APIC_ID=0
205 ## Build code to setup a generic IOAPIC
207 default CONFIG_IOAPIC=1
210 ## Clean up the motherboard id strings
212 default MAINBOARD_PART_NUMBER="ms9282"
213 default MAINBOARD_VENDOR="MSI"
214 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
215 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
218 ### coreboot layout values
221 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
222 default ROM_IMAGE_SIZE = 65536
225 ## Use a small 8K stack
227 default STACK_SIZE=0x2000
230 ## Use a small 16K heap
232 default HEAP_SIZE=0x4000
235 ## Only use the option table in a normal image
237 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
240 ## Coreboot C code runs at this location in RAM
242 default _RAMBASE=0x00004000
245 ## Load the payload from the ROM
247 default CONFIG_ROM_PAYLOAD = 1
250 ### Defaults of options that you may want to override in the target config file
254 ## The default compiler
256 default CC="$(CROSS_COMPILE)gcc -m32"
260 ## Disable the gdb stub by default
262 default CONFIG_GDB_STUB=0
265 ## The Serial Console
267 default CONFIG_USE_PRINTK_IN_CAR=1
269 # To Enable the Serial Console
270 default CONFIG_CONSOLE_SERIAL8250=1
272 ## Select the serial console baud rate
273 default TTYS0_BAUD=115200
274 #default TTYS0_BAUD=57600
275 #default TTYS0_BAUD=38400
276 #default TTYS0_BAUD=19200
277 #default TTYS0_BAUD=9600
278 #default TTYS0_BAUD=4800
279 #default TTYS0_BAUD=2400
280 #default TTYS0_BAUD=1200
282 # Select the serial console base port
283 default TTYS0_BASE=0x3f8
285 # Select the serial protocol
286 # This defaults to 8 data bits, 1 stop bit, and no parity
287 default TTYS0_LCS=0x3
290 ### Select the coreboot loglevel
292 ## EMERG 1 system is unusable
293 ## ALERT 2 action must be taken immediately
294 ## CRIT 3 critical conditions
295 ## ERR 4 error conditions
296 ## WARNING 5 warning conditions
297 ## NOTICE 6 normal but significant condition
298 ## INFO 7 informational
299 ## DEBUG 8 debug-level messages
300 ## SPEW 9 Way too many details
302 ## Request this level of debugging output
303 default DEFAULT_CONSOLE_LOGLEVEL=8
304 ## At a maximum only compile in this level of debugging
305 default MAXIMUM_CONSOLE_LOGLEVEL=8
308 ## Select power on after power fail setting
309 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
316 default CONFIG_CBFS=0