Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / msi / ms9282 / Kconfig
1 if BOARD_MSI_MS9282
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_F
7         select DIMM_DDR2
8         select DIMM_REGISTERED
9         select NORTHBRIDGE_AMD_AMDK8
10         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
11         select SOUTHBRIDGE_NVIDIA_MCP55
12         select SUPERIO_WINBOND_W83627EHG
13         select HAVE_BUS_CONFIG
14         select HAVE_OPTION_TABLE
15         select HAVE_PIRQ_TABLE
16         select HAVE_MP_TABLE
17         select HAVE_HARD_RESET
18         select K8_REV_F_SUPPORT
19         select BOARD_ROMSIZE_KB_512
20         select RAMINIT_SYSINFO
21         select QRANK_DIMM_SUPPORT
22
23 config MAINBOARD_DIR
24         string
25         default msi/ms9282
26
27 config DCACHE_RAM_BASE
28         hex
29         default 0xcc000
30
31 config DCACHE_RAM_SIZE
32         hex
33         default 0x04000
34
35 config DCACHE_RAM_GLOBAL_VAR_SIZE
36         hex
37         default 0x01000
38
39 config APIC_ID_OFFSET
40         hex
41         default 0x10
42
43 config SB_HT_CHAIN_ON_BUS0
44         int
45         default 1
46
47 config MAINBOARD_PART_NUMBER
48         string
49         default "MS-9282"
50
51 config PCI_64BIT_PREF_MEM
52         bool
53         default n
54
55 config MAX_CPUS
56         int
57         default 4
58
59 config MAX_PHYSICAL_CPUS
60         int
61         default 2
62
63 config HT_CHAIN_UNITID_BASE
64         hex
65         default 0x0
66
67 config HT_CHAIN_END_UNITID_BASE
68         hex
69         default 0x20
70
71 config SERIAL_CPU_INIT
72         bool
73         default n
74
75 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
76         hex
77         default 0x1462
78
79 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
80         hex
81         default 0x9282
82
83 config IRQ_SLOT_COUNT
84         int
85         default 11
86
87 endif # BOARD_MSI_MS9282