src/mainboard/msi/ms9185/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2006 MSI
   9  * Written by bxshi <bingxunshi@gmail.com> for MSI.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  38 #include "northbridge/amd/amdk8/raminit.h"
  39 #include "cpu/amd/model_fxx/apic_timer.c"
  40 #include "lib/delay.c"
  41 #include <reset.h>
  42 #include "cpu/x86/lapic/boot_cpu.c"
  43 #include "northbridge/amd/amdk8/reset_test.c"
  44 #include "northbridge/amd/amdk8/debug.c"
  45 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  52 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  55
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58 #define SMBUS_SWITCH1 0x70
  59 #define SMBUS_SWITCH2 0x72
  60         unsigned device = (ctrl->channel0[0]) >> 8;
  61         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  62         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  63 }
  64
  65 #if 0
  66 static inline void change_i2c_mux(unsigned device)
  67 {
  68 #define SMBUS_SWITCH1 0x70
  69 #define SMBUS_SWITCH2 0x72
  70         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  71         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  72 }
  73 #endif
  74
  75 static inline int spd_read_byte(unsigned device, unsigned address)
  76 {
  77         return smbus_read_byte(device, address);
  78 }
  79
  80 #include "northbridge/amd/amdk8/amdk8_f.h"
  81 #include "northbridge/amd/amdk8/incoherent_ht.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "northbridge/amd/amdk8/raminit_f.c"
  84 #include "lib/generic_sdram.c"
  85 #include "resourcemap.c"
  86 #include "cpu/amd/dualcore/dualcore.c"
  87 #include <spd.h>
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90 #include "cpu/amd/model_fxx/fidvid.c"
  91 #include "northbridge/amd/amdk8/early_ht.c"
  92
  93 #define RC0 (0x10<<8)
  94 #define RC1 (0x01<<8)
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98        static const uint16_t spd_addr[] = {
  99                       //first node
 100                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
 101                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
 102                        //second node
 103                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 104                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 105        };
 106
 107         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
 108                 CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 109
 110         int needs_reset;
 111         unsigned bsp_apicid = 0;
 112
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0 */
 115                 /* Allow the HT devices to be found */
 116                 enumerate_ht_chain();
 117                 bcm5785_enable_lpc();
 118                 //enable RTC
 119                 pc87417_enable_dev(RTC_DEV);
 120         }
 121
 122         if (bist == 0)
 123                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 124
 125         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 130
 131        /* Halt if there was a built in self test failure */
 132        report_bist_failure(bist);
 133
 134        printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 135
 136        setup_ms9185_resource_map();
 137 #if 0
 138        dump_pci_device(PCI_DEV(0, 0x18, 0));
 139        dump_pci_device(PCI_DEV(0, 0x19, 0));
 140 #endif
 141
 142        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 143
 144        setup_coherent_ht_domain();
 145
 146        wait_all_core0_started();
 147 #if CONFIG_LOGICAL_CPUS==1
 148         // It is said that we should start core1 after all core0 launched
 149        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 150         * So here need to make sure last core0 is started, esp for two way system,
 151         * (there may be apic id conflicts in that case)
 152         */
 153         start_other_cores();
 154 //bx_a010-     wait_all_other_cores_started(bsp_apicid);
 155 #endif
 156
 157        /* it will set up chains and store link pair for optimization later */
 158        ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 159
 160        bcm5785_early_setup();
 161
 162 #if 0
 163        //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 164         needs_reset = optimize_link_coherent_ht();
 165         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 166 #endif
 167
 168 #if CONFIG_SET_FIDVID
 169         {
 170                 msr_t msr;
 171                 msr=rdmsr(0xc0010042);
 172                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 173         }
 174         enable_fid_change();
 175         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 176         init_fidvid_bsp(bsp_apicid);
 177         // show final fid and vid
 178         {
 179                 msr_t msr;
 180                 msr=rdmsr(0xc0010042);
 181                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 182         }
 183 #endif
 184
 185 #if 1
 186        needs_reset = optimize_link_coherent_ht();
 187        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 188
 189         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 190         if (needs_reset) {
 191                 print_info("ht reset -\n");
 192                 soft_reset();
 193         }
 194 #endif
 195        allow_all_aps_stop(bsp_apicid);
 196
 197         //It's the time to set ctrl in sysinfo now;
 198        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 199
 200        enable_smbus();
 201
 202 #if 0
 203        int i;
 204        for(i=0;i<2;i++) {
 205                activate_spd_rom(sysinfo->ctrl+i);
 206                dump_smbus_registers();
 207        }
 208 #endif
 209
 210 #if 0
 211        int i;
 212         for(i=1;i<256;i<<=1) {
 213                 change_i2c_mux(i);
 214                 dump_smbus_registers();
 215         }
 216 #endif
 217
 218        //do we need apci timer, tsc...., only debug need it for better output
 219         /* all ap stopped? */
 220 //        init_timer(); // Need to use TMICT to synconize FID/VID
 221
 222        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 223
 224 #if 0
 225         print_pci_devices();
 226 #endif
 227
 228 #if 0
 229 //        dump_pci_devices();
 230         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 231        dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 232 #endif
 233
 234        post_cache_as_ram();
 235 }