src/mainboard/msi/ms9185/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2006 MSI
   9  * Written by bxshi <bingxunshi@gmail.com> for MSI.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <console/console.h>
  36
  37 #include <cpu/amd/model_fxx_rev.h>
  38 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  39 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  40 #include "northbridge/amd/amdk8/raminit.h"
  41 #include "cpu/amd/model_fxx/apic_timer.c"
  42 #include "lib/delay.c"
  43 #include <reset.h>
  44
  45 #include "cpu/x86/lapic/boot_cpu.c"
  46 #include "northbridge/amd/amdk8/reset_test.c"
  47 #include "northbridge/amd/amdk8/debug.c"
  48 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  49 #include "cpu/x86/mtrr/earlymtrr.c"
  50 #include "cpu/x86/bist.h"
  51
  52 #include "northbridge/amd/amdk8/setup_resource_map.c"
  53
  54 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  55 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  56 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  57
  58 static void memreset(int controllers, const struct mem_controller *ctrl)
  59 {
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64 #define SMBUS_SWITCH1 0x70
  65 #define SMBUS_SWITCH2 0x72
  66         unsigned device = (ctrl->channel0[0]) >> 8;
  67         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  68         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  69 }
  70
  71 #if 0
  72 static inline void change_i2c_mux(unsigned device)
  73 {
  74 #define SMBUS_SWITCH1 0x70
  75 #define SMBUS_SWITCH2 0x72
  76         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  77         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  78 }
  79 #endif
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #include "northbridge/amd/amdk8/amdk8_f.h"
  87 #include "northbridge/amd/amdk8/incoherent_ht.c"
  88 #include "northbridge/amd/amdk8/coherent_ht.c"
  89 #include "northbridge/amd/amdk8/raminit_f.c"
  90 #include "lib/generic_sdram.c"
  91
  92  /* msi does not want the default */
  93 #include "resourcemap.c"
  94
  95 #include "cpu/amd/dualcore/dualcore.c"
  96 #include <spd.h>
  97
  98 #define RC0 (0x10<<8)
  99 #define RC1 (0x01<<8)
 100
 101 #include "cpu/amd/car/post_cache_as_ram.c"
 102
 103 #include "cpu/amd/model_fxx/init_cpus.c"
 104
 105 #include "cpu/amd/model_fxx/fidvid.c"
 106
 107 #include "northbridge/amd/amdk8/early_ht.c"
 108
 109 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 110 {
 111        static const uint16_t spd_addr[] = {
 112                       //first node
 113                        RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
 114                        RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
 115                        //second node
 116                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 117                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 118        };
 119
 120         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
 121                 CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 122
 123         int needs_reset;
 124         unsigned bsp_apicid = 0;
 125
 126         if (!cpu_init_detectedx && boot_cpu()) {
 127                 /* Nothing special needs to be done to find bus 0 */
 128                 /* Allow the HT devices to be found */
 129
 130                 enumerate_ht_chain();
 131
 132                 bcm5785_enable_rom();
 133
 134                 bcm5785_enable_lpc();
 135
 136                 //enable RTC
 137                 pc87417_enable_dev(RTC_DEV);
 138         }
 139
 140         if (bist == 0) {
 141                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 142         }
 143
 144 //     post_code(0x32);
 145
 146        pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 147         uart_init();
 148         console_init();
 149
 150 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 151
 152        /* Halt if there was a built in self test failure */
 153        report_bist_failure(bist);
 154
 155         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 156
 157        setup_ms9185_resource_map();
 158 #if 0
 159         dump_pci_device(PCI_DEV(0, 0x18, 0));
 160        dump_pci_device(PCI_DEV(0, 0x19, 0));
 161 #endif
 162
 163        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 164
 165        setup_coherent_ht_domain();
 166
 167        wait_all_core0_started();
 168 #if CONFIG_LOGICAL_CPUS==1
 169         // It is said that we should start core1 after all core0 launched
 170        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 171         * So here need to make sure last core0 is started, esp for two way system,
 172         * (there may be apic id conflicts in that case)
 173         */
 174         start_other_cores();
 175 //bx_a010-     wait_all_other_cores_started(bsp_apicid);
 176 #endif
 177
 178        /* it will set up chains and store link pair for optimization later */
 179         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 180
 181        bcm5785_early_setup();
 182
 183 #if 0
 184        //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 185         needs_reset = optimize_link_coherent_ht();
 186         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 187 #endif
 188
 189 #if CONFIG_SET_FIDVID
 190
 191         {
 192                 msr_t msr;
 193                 msr=rdmsr(0xc0010042);
 194                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 195
 196         }
 197
 198        enable_fid_change();
 199
 200        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 201
 202         init_fidvid_bsp(bsp_apicid);
 203
 204         // show final fid and vid
 205         {
 206                 msr_t msr;
 207                 msr=rdmsr(0xc0010042);
 208                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 209
 210         }
 211 #endif
 212
 213 #if 1
 214        needs_reset = optimize_link_coherent_ht();
 215        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 216
 217         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 218         if (needs_reset) {
 219                 print_info("ht reset -\n");
 220                 soft_reset();
 221         }
 222 #endif
 223        allow_all_aps_stop(bsp_apicid);
 224
 225         //It's the time to set ctrl in sysinfo now;
 226        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 227
 228        enable_smbus();
 229
 230 #if 0
 231        int i;
 232        for(i=0;i<2;i++) {
 233                activate_spd_rom(sysinfo->ctrl+i);
 234                dump_smbus_registers();
 235        }
 236 #endif
 237
 238 #if 0
 239        int i;
 240         for(i=1;i<256;i<<=1) {
 241                 change_i2c_mux(i);
 242                 dump_smbus_registers();
 243         }
 244 #endif
 245
 246        //do we need apci timer, tsc...., only debug need it for better output
 247         /* all ap stopped? */
 248 //        init_timer(); // Need to use TMICT to synconize FID/VID
 249
 250        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 251
 252 #if 0
 253         print_pci_devices();
 254 #endif
 255
 256 #if 0
 257 //        dump_pci_devices();
 258         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 259        dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 260 #endif
 261
 262        post_cache_as_ram();
 263
 264 }
 265