2 * This file is part of the coreboot project.
4 * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
6 * Copyright (C) 2006 AMD
7 * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
9 * Copyright (C) 2006 MSI
10 * Written by bxshi <bingxunshi@gmail.com> for MSI.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <console/console.h>
28 #include <arch/smp/mpspec.h>
30 #include <device/pci.h>
33 #if CONFIG_LOGICAL_CPUS==1
34 #include <cpu/amd/multicore.h>
37 #include <cpu/amd/amdk8_sysconf.h>
39 #include "mb_sysconf.h"
43 static void *smp_write_config_table(void *v)
45 static const char sig[4] = "PCMP";
46 static const char oem[8] = "COREBOOT";
47 static const char productid[12] = "MS9185 ";
48 struct mp_config_table *mc;
50 unsigned char bus_num;
52 struct mb_sysconf_t *m;
54 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
55 memset(mc, 0, sizeof(*mc));
57 memcpy(mc->mpc_signature, sig, sizeof(sig));
58 mc->mpc_length = sizeof(*mc); /* initially just the header */
60 mc->mpc_checksum = 0; /* not yet computed */
61 memcpy(mc->mpc_oem, oem, sizeof(oem));
62 memcpy(mc->mpc_productid, productid, sizeof(productid));
65 mc->mpc_entry_count = 0; /* No entries yet... */
66 mc->mpc_lapic = LAPIC_ADDR;
71 smp_write_processors(mc);
77 /* define bus and isa numbers */
78 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
79 smp_write_bus(mc, bus_num, "PCI ");
81 smp_write_bus(mc, m->bus_isa, "ISA ");
83 /*I/O APICs: APIC ID Version State Address*/
88 dev = dev_find_device(0x1166, 0x0235, dev);
90 res = find_resource(dev, PCI_BASE_ADDRESS_0);
92 smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
99 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
102 outb(0x02, 0xc00); outb(0x0e, 0xc01);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
107 outb(0x07, 0xc00); outb(0x0f, 0xc01);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
111 outb(0x01, 0xc00); outb(0x0a, 0xc01);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
119 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
122 dev = dev_find_device(0x1166, 0x0205, 0);
125 dword = pci_read_config32(dev, 0x6c);
126 dword |= (1<<4); // enable interrupts
127 pci_write_config32(dev, 0x6c, dword);
131 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
132 // AIC 8130 Galileo Technology...
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
138 //pci slot (on bcm5785)
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
174 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
175 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
176 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
177 /* There is no extension information... */
179 /* Compute the checksums */
180 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
181 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
182 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
183 mc, smp_next_mpe_entry(mc));
184 return smp_next_mpe_entry(mc);
187 unsigned long write_smp_table(unsigned long addr)
190 v = smp_write_floating_table(addr);
191 return (unsigned long)smp_write_config_table(v);