2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
6 * Copyright (C) 2006 AMD
7 * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
9 * Copyright (C) 2006 MSI
10 * Written by bxshi <bingxunshi@gmail.com> for MSI.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <console/console.h>
28 #include <arch/smp/mpspec.h>
30 #include <device/pci.h>
33 #if CONFIG_LOGICAL_CPUS==1
34 #include <cpu/amd/dualcore.h>
37 #include <cpu/amd/amdk8_sysconf.h>
39 #include "mb_sysconf.h"
41 extern void get_bus_conf(void);
43 void *smp_write_config_table(void *v)
45 static const char sig[4] = "PCMP";
46 static const char oem[3] = "MSI";
47 static const char productid[6] = "MS9185 ";
48 struct mp_config_table *mc;
50 unsigned char bus_num;
52 struct mb_sysconf_t *m;
54 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
55 memset(mc, 0, sizeof(*mc));
57 memcpy(mc->mpc_signature, sig, sizeof(sig));
58 mc->mpc_length = sizeof(*mc); /* initially just the header */
60 mc->mpc_checksum = 0; /* not yet computed */
61 memcpy(mc->mpc_oem, oem, sizeof(oem));
62 memcpy(mc->mpc_productid, productid, sizeof(productid));
65 mc->mpc_entry_count = 0; /* No entries yet... */
66 mc->mpc_lapic = LAPIC_ADDR;
71 smp_write_processors(mc);
77 /* define bus and isa numbers */
78 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
79 smp_write_bus(mc, bus_num, "PCI ");
81 smp_write_bus(mc, m->bus_isa, "ISA ");
83 /*I/O APICs: APIC ID Version State Address*/
89 dev = dev_find_device(0x1166, 0x0235, dev);
91 res = find_resource(dev, PCI_BASE_ADDRESS_0);
93 smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
100 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
101 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_bcm5785[0], 0x0);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_bcm5785[0], 0x1);
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_bcm5785[0], 0x2);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_bcm5785[0], 0x3);
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_bcm5785[0], 0x4);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_bcm5785[0], 0x5);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_bcm5785[0], 0x6);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_bcm5785[0], 0x7);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_bcm5785[0], 0x8);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_bcm5785[0], 0x9);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_bcm5785[0], 0xc);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_bcm5785[0], 0xd);
115 outb(0x02, 0xc00); outb(0x0e, 0xc01);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
120 outb(0x07, 0xc00); outb(0x0f, 0xc01);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
124 outb(0x01, 0xc00); outb(0x0a, 0xc01);
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
132 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
135 dev = dev_find_device(0x1166, 0x0205, 0);
138 dword = pci_read_config32(dev, 0x6c);
139 dword |= (1<<4); // enable interrupts
140 pci_write_config32(dev, 0x6c, dword);
144 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
145 // AIC 8130 Galileo Technology...
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
151 //pci slot (on bcm5785)
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
187 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
188 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
189 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
190 /* There is no extension information... */
192 /* Compute the checksums */
193 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
194 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
195 printk_debug("Wrote the mp table end at: %p - %p\n",
196 mc, smp_next_mpe_entry(mc));
197 return smp_next_mpe_entry(mc);
200 unsigned long write_smp_table(unsigned long addr)
203 v = smp_write_floating_table(addr);
204 return (unsigned long)smp_write_config_table(v);