2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by bxshi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 uses CONFIG_GENERATE_MP_TABLE
26 uses CONFIG_GENERATE_PIRQ_TABLE
27 uses CONFIG_GENERATE_ACPI_TABLES
28 uses CONFIG_HAVE_ACPI_RESUME
29 uses CONFIG_ACPI_SSDTX_NUM
30 uses CONFIG_USE_FALLBACK_IMAGE
31 uses CONFIG_HAVE_FALLBACK_BOOT
32 uses CONFIG_HAVE_HARD_RESET
33 uses CONFIG_IRQ_SLOT_COUNT
34 uses CONFIG_HAVE_OPTION_TABLE
36 uses CONFIG_MAX_PHYSICAL_CPUS
37 uses CONFIG_LOGICAL_CPUS
40 uses CONFIG_FALLBACK_SIZE
42 uses CONFIG_ROM_SECTION_SIZE
43 uses CONFIG_ROM_IMAGE_SIZE
44 uses CONFIG_ROM_SECTION_SIZE
45 uses CONFIG_ROM_SECTION_OFFSET
46 uses CONFIG_ROM_PAYLOAD
47 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
48 uses CONFIG_PRECOMPRESSED_PAYLOAD
50 uses CONFIG_XIP_ROM_SIZE
51 uses CONFIG_XIP_ROM_BASE
52 uses CONFIG_STACK_SIZE
54 uses CONFIG_USE_OPTION_TABLE
55 uses CONFIG_LB_CKS_RANGE_START
56 uses CONFIG_LB_CKS_RANGE_END
57 uses CONFIG_LB_CKS_LOC
58 uses CONFIG_MAINBOARD_PART_NUMBER
59 uses CONFIG_MAINBOARD_VENDOR
61 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
62 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
63 uses COREBOOT_EXTRA_VERSION
65 uses CONFIG_TTYS0_BAUD
66 uses CONFIG_TTYS0_BASE
68 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
69 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
70 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
71 uses CONFIG_CONSOLE_SERIAL8250
72 uses CONFIG_HAVE_INIT_TIMER
75 uses CONFIG_CROSS_COMPILE
79 uses CONFIG_CONSOLE_VGA
80 uses CONFIG_PCI_ROM_RUN
81 uses CONFIG_HW_MEM_HOLE_SIZEK
82 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
83 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
85 uses CONFIG_HT_CHAIN_UNITID_BASE
86 uses CONFIG_HT_CHAIN_END_UNITID_BASE
87 uses CONFIG_SB_HT_CHAIN_ON_BUS0
88 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
90 uses CONFIG_USE_DCACHE_RAM
91 uses CONFIG_DCACHE_RAM_BASE
92 uses CONFIG_DCACHE_RAM_SIZE
93 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
96 uses CONFIG_SERIAL_CPU_INIT
98 uses CONFIG_ENABLE_APIC_EXT_ID
99 uses CONFIG_APIC_ID_OFFSET
100 uses CONFIG_LIFT_BSP_APIC_ID
102 uses CONFIG_PCI_64BIT_PREF_MEM
105 uses CONFIG_USE_PRINTK_IN_CAR
112 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
114 default CONFIG_ROM_SIZE=524288
117 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
118 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
121 default CONFIG_RAMTOP=2048*1024
124 ## Build code for the fallback boot
126 default CONFIG_HAVE_FALLBACK_BOOT=1
129 ## Build code to reset the motherboard from coreboot
131 default CONFIG_HAVE_HARD_RESET=1
134 ## Build code to export a programmable irq routing table
136 default CONFIG_GENERATE_PIRQ_TABLE=1
137 default CONFIG_IRQ_SLOT_COUNT=11
140 ## Build code to export an x86 MP table
141 ## Useful for specifying IRQ routing values
143 default CONFIG_GENERATE_MP_TABLE=1
145 ## ACPI tables will be included
146 #default CONFIG_GENERATE_ACPI_TABLES=1
148 #default CONFIG_ACPI_SSDTX_NUM=1
151 ## Build code to export a CMOS option table
153 default CONFIG_HAVE_OPTION_TABLE=1
156 ## Move the default coreboot cmos range off of AMD RTC registers
158 default CONFIG_LB_CKS_RANGE_START=49
159 default CONFIG_LB_CKS_RANGE_END=122
160 default CONFIG_LB_CKS_LOC=123
163 ## Build code for SMP support
164 ## Only worry about 2 micro processors
167 default CONFIG_MAX_CPUS=4
168 default CONFIG_MAX_PHYSICAL_CPUS=2
169 default CONFIG_LOGICAL_CPUS=1
171 default CONFIG_SERIAL_CPU_INIT=0
173 default CONFIG_ENABLE_APIC_EXT_ID=0
174 default CONFIG_APIC_ID_OFFSET=0x8
175 default CONFIG_LIFT_BSP_APIC_ID=1
177 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
179 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
181 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
183 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
185 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
186 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
188 #Opteron K8 1G HT Support
189 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
192 default CONFIG_CONSOLE_VGA=1
193 default CONFIG_PCI_ROM_RUN=1
195 #HT Unit ID offset, default is 1, the typical one
196 default CONFIG_HT_CHAIN_UNITID_BASE=0x06
198 #real SB Unit ID, default is 0x20, mean dont touch it at last
199 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
201 #make the SB HT chain on bus 0, default is not (0)
202 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
204 #only offset for SB chain?, default is yes(1)
205 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
207 #allow capable device use that above 4G
208 #default CONFIG_PCI_64BIT_PREF_MEM=1
211 ## enable CACHE_AS_RAM specifics
213 default CONFIG_USE_DCACHE_RAM=1
214 default CONFIG_DCACHE_RAM_BASE=0xcc000
215 default CONFIG_DCACHE_RAM_SIZE=0x04000
216 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
217 default CONFIG_USE_INIT=0
220 ## Build code to setup a generic IOAPIC
222 default CONFIG_IOAPIC=1
225 ## Clean up the motherboard id strings
227 default CONFIG_MAINBOARD_PART_NUMBER="MS9185"
228 default CONFIG_MAINBOARD_VENDOR="MSI"
229 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
230 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
233 ### coreboot layout values
236 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
237 default CONFIG_ROM_IMAGE_SIZE = 65536
240 ## Use a small 8K stack
242 default CONFIG_STACK_SIZE=0x2000
245 ## Use a small 32K heap
247 default CONFIG_HEAP_SIZE=0x8000
250 ## Only use the option table in a normal image
252 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
255 ## Coreboot C code runs at this location in RAM
257 default CONFIG_RAMBASE=0x00100000
260 ## Load the payload from the ROM
262 default CONFIG_ROM_PAYLOAD = 1
265 ### Defaults of options that you may want to override in the target config file
269 ## The default compiler
271 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
275 ## Disable the gdb stub by default
277 default CONFIG_GDB_STUB=0
280 ## The Serial Console
282 default CONFIG_USE_PRINTK_IN_CAR=1
284 # To Enable the Serial Console
285 default CONFIG_CONSOLE_SERIAL8250=1
287 ## Select the serial console baud rate
288 default CONFIG_TTYS0_BAUD=115200
289 #default CONFIG_TTYS0_BAUD=57600
290 #default CONFIG_TTYS0_BAUD=38400
291 #default CONFIG_TTYS0_BAUD=19200
292 #default CONFIG_TTYS0_BAUD=9600
293 #default CONFIG_TTYS0_BAUD=4800
294 #default CONFIG_TTYS0_BAUD=2400
295 #default CONFIG_TTYS0_BAUD=1200
297 # Select the serial console base port
298 default CONFIG_TTYS0_BASE=0x3f8
300 # Select the serial protocol
301 # This defaults to 8 data bits, 1 stop bit, and no parity
302 default CONFIG_TTYS0_LCS=0x3
305 ### Select the coreboot loglevel
307 ## EMERG 1 system is unusable
308 ## ALERT 2 action must be taken immediately
309 ## CRIT 3 critical conditions
310 ## ERR 4 error conditions
311 ## WARNING 5 warning conditions
312 ## NOTICE 6 normal but significant condition
313 ## INFO 7 informational
314 ## CONFIG_DEBUG 8 debug-level messages
315 ## SPEW 9 Way too many details
317 ## Request this level of debugging output
318 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
319 ## At a maximum only compile in this level of debugging
320 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
323 ## Select power on after power fail setting
324 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"