2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by bxshi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 uses CONFIG_HAVE_MP_TABLE
27 uses CONFIG_HAVE_PIRQ_TABLE
28 uses CONFIG_HAVE_ACPI_TABLES
29 uses CONFIG_HAVE_ACPI_RESUME
30 uses CONFIG_ACPI_SSDTX_NUM
31 uses CONFIG_USE_FALLBACK_IMAGE
32 uses CONFIG_HAVE_FALLBACK_BOOT
33 uses CONFIG_HAVE_HARD_RESET
34 uses CONFIG_IRQ_SLOT_COUNT
35 uses CONFIG_HAVE_OPTION_TABLE
37 uses CONFIG_MAX_PHYSICAL_CPUS
38 uses CONFIG_LOGICAL_CPUS
41 uses CONFIG_FALLBACK_SIZE
43 uses CONFIG_ROM_SECTION_SIZE
44 uses CONFIG_ROM_IMAGE_SIZE
45 uses CONFIG_ROM_SECTION_SIZE
46 uses CONFIG_ROM_SECTION_OFFSET
47 uses CONFIG_ROM_PAYLOAD
48 uses CONFIG_ROM_PAYLOAD_START
49 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
50 uses CONFIG_PRECOMPRESSED_PAYLOAD
51 uses CONFIG_PAYLOAD_SIZE
53 uses CONFIG_XIP_ROM_SIZE
54 uses CONFIG_XIP_ROM_BASE
55 uses CONFIG_STACK_SIZE
57 uses CONFIG_USE_OPTION_TABLE
58 uses CONFIG_LB_CKS_RANGE_START
59 uses CONFIG_LB_CKS_RANGE_END
60 uses CONFIG_LB_CKS_LOC
61 uses CONFIG_MAINBOARD_PART_NUMBER
62 uses CONFIG_MAINBOARD_VENDOR
64 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
65 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
66 uses COREBOOT_EXTRA_VERSION
68 uses CONFIG_TTYS0_BAUD
69 uses CONFIG_TTYS0_BASE
71 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
72 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
73 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 uses CONFIG_CONSOLE_SERIAL8250
75 uses CONFIG_HAVE_INIT_TIMER
78 uses CONFIG_CROSS_COMPILE
82 uses CONFIG_CONSOLE_VGA
83 uses CONFIG_PCI_ROM_RUN
84 uses CONFIG_HW_MEM_HOLE_SIZEK
85 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
86 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
88 uses CONFIG_HT_CHAIN_UNITID_BASE
89 uses CONFIG_HT_CHAIN_END_UNITID_BASE
90 uses CONFIG_SB_HT_CHAIN_ON_BUS0
91 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
93 uses CONFIG_USE_DCACHE_RAM
94 uses CONFIG_DCACHE_RAM_BASE
95 uses CONFIG_DCACHE_RAM_SIZE
96 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
99 uses CONFIG_SERIAL_CPU_INIT
101 uses CONFIG_ENABLE_APIC_EXT_ID
102 uses CONFIG_APIC_ID_OFFSET
103 uses CONFIG_LIFT_BSP_APIC_ID
105 uses CONFIG_PCI_64BIT_PREF_MEM
107 uses CONFIG_LB_MEM_TOPK
108 uses CONFIG_USE_PRINTK_IN_CAR
115 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
117 default CONFIG_ROM_SIZE=524288
120 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
121 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
124 default CONFIG_LB_MEM_TOPK=2048
127 ## Build code for the fallback boot
129 default CONFIG_HAVE_FALLBACK_BOOT=1
132 ## Build code to reset the motherboard from coreboot
134 default CONFIG_HAVE_HARD_RESET=1
137 ## Build code to export a programmable irq routing table
139 default CONFIG_HAVE_PIRQ_TABLE=1
140 default CONFIG_IRQ_SLOT_COUNT=11
143 ## Build code to export an x86 MP table
144 ## Useful for specifying IRQ routing values
146 default CONFIG_HAVE_MP_TABLE=1
148 ## ACPI tables will be included
149 #default CONFIG_HAVE_ACPI_TABLES=1
151 #default CONFIG_ACPI_SSDTX_NUM=1
154 ## Build code to export a CMOS option table
156 default CONFIG_HAVE_OPTION_TABLE=1
159 ## Move the default coreboot cmos range off of AMD RTC registers
161 default CONFIG_LB_CKS_RANGE_START=49
162 default CONFIG_LB_CKS_RANGE_END=122
163 default CONFIG_LB_CKS_LOC=123
166 ## Build code for SMP support
167 ## Only worry about 2 micro processors
170 default CONFIG_MAX_CPUS=4
171 default CONFIG_MAX_PHYSICAL_CPUS=2
172 default CONFIG_LOGICAL_CPUS=1
174 default CONFIG_SERIAL_CPU_INIT=0
176 default CONFIG_ENABLE_APIC_EXT_ID=0
177 default CONFIG_APIC_ID_OFFSET=0x8
178 default CONFIG_LIFT_BSP_APIC_ID=1
180 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
182 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
184 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
186 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
188 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
189 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
191 #Opteron K8 1G HT Support
192 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
195 default CONFIG_CONSOLE_VGA=1
196 default CONFIG_PCI_ROM_RUN=1
198 #HT Unit ID offset, default is 1, the typical one
199 default CONFIG_HT_CHAIN_UNITID_BASE=0x06
201 #real SB Unit ID, default is 0x20, mean dont touch it at last
202 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
204 #make the SB HT chain on bus 0, default is not (0)
205 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
207 #only offset for SB chain?, default is yes(1)
208 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
210 #allow capable device use that above 4G
211 #default CONFIG_PCI_64BIT_PREF_MEM=1
214 ## enable CACHE_AS_RAM specifics
216 default CONFIG_USE_DCACHE_RAM=1
217 default CONFIG_DCACHE_RAM_BASE=0xcc000
218 default CONFIG_DCACHE_RAM_SIZE=0x04000
219 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
220 default CONFIG_USE_INIT=0
223 ## Build code to setup a generic IOAPIC
225 default CONFIG_IOAPIC=1
228 ## Clean up the motherboard id strings
230 default CONFIG_MAINBOARD_PART_NUMBER="MS9185"
231 default CONFIG_MAINBOARD_VENDOR="MSI"
232 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
233 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
236 ### coreboot layout values
239 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
240 default CONFIG_ROM_IMAGE_SIZE = 65536
243 ## Use a small 8K stack
245 default CONFIG_STACK_SIZE=0x2000
248 ## Use a small 32K heap
250 default CONFIG_HEAP_SIZE=0x8000
253 ## Only use the option table in a normal image
255 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
258 ## Coreboot C code runs at this location in RAM
260 default CONFIG_RAMBASE=0x00100000
263 ## Load the payload from the ROM
265 default CONFIG_ROM_PAYLOAD = 1
268 ### Defaults of options that you may want to override in the target config file
272 ## The default compiler
274 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
278 ## Disable the gdb stub by default
280 default CONFIG_GDB_STUB=0
283 ## The Serial Console
285 default CONFIG_USE_PRINTK_IN_CAR=1
287 # To Enable the Serial Console
288 default CONFIG_CONSOLE_SERIAL8250=1
290 ## Select the serial console baud rate
291 default CONFIG_TTYS0_BAUD=115200
292 #default CONFIG_TTYS0_BAUD=57600
293 #default CONFIG_TTYS0_BAUD=38400
294 #default CONFIG_TTYS0_BAUD=19200
295 #default CONFIG_TTYS0_BAUD=9600
296 #default CONFIG_TTYS0_BAUD=4800
297 #default CONFIG_TTYS0_BAUD=2400
298 #default CONFIG_TTYS0_BAUD=1200
300 # Select the serial console base port
301 default CONFIG_TTYS0_BASE=0x3f8
303 # Select the serial protocol
304 # This defaults to 8 data bits, 1 stop bit, and no parity
305 default CONFIG_TTYS0_LCS=0x3
308 ### Select the coreboot loglevel
310 ## EMERG 1 system is unusable
311 ## ALERT 2 action must be taken immediately
312 ## CRIT 3 critical conditions
313 ## ERR 4 error conditions
314 ## WARNING 5 warning conditions
315 ## NOTICE 6 normal but significant condition
316 ## INFO 7 informational
317 ## CONFIG_DEBUG 8 debug-level messages
318 ## SPEW 9 Way too many details
320 ## Request this level of debugging output
321 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
322 ## At a maximum only compile in this level of debugging
323 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
326 ## Select power on after power fail setting
327 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
334 default CONFIG_CBFS=1