2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #if CONFIG_K8_REV_F_SUPPORT == 1
24 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
29 #include <device/pci_def.h>
30 #include <device/pci_ids.h>
32 #include <device/pnp_def.h>
33 #include <arch/romcc_io.h>
34 #include <cpu/x86/lapic.h>
35 #include <pc80/mc146818rtc.h>
36 #include <console/console.h>
37 #include <cpu/amd/model_fxx_rev.h>
38 #include "southbridge/nvidia/mcp55/early_smbus.c"
39 #include "northbridge/amd/amdk8/raminit.h"
40 #include "cpu/amd/model_fxx/apic_timer.c"
41 #include "lib/delay.c"
44 #include "cpu/x86/lapic/boot_cpu.c"
45 #include "northbridge/amd/amdk8/reset_test.c"
46 #include "superio/winbond/w83627ehg/early_serial.c"
47 #include "superio/winbond/w83627ehg/early_init.c"
48 #include "cpu/x86/bist.h"
49 #include "northbridge/amd/amdk8/debug.c"
50 #include "cpu/x86/mtrr/earlymtrr.c"
51 #include "northbridge/amd/amdk8/setup_resource_map.c"
52 #include "southbridge/nvidia/mcp55/early_ctrl.c"
54 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
56 static void memreset(int controllers, const struct mem_controller *ctrl) {}
57 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
59 static inline int spd_read_byte(unsigned int device, unsigned int address)
61 return smbus_read_byte(device, address);
64 #include "northbridge/amd/amdk8/f.h"
65 #include "northbridge/amd/amdk8/incoherent_ht.c"
66 #include "northbridge/amd/amdk8/coherent_ht.c"
67 #include "northbridge/amd/amdk8/raminit_f.c"
68 #include "lib/generic_sdram.c"
69 #include "resourcemap.c"
70 #include "cpu/amd/dualcore/dualcore.c"
72 #define MCP55_MB_SETUP \
73 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
74 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
75 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
76 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
77 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
78 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
80 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
81 #include "southbridge/nvidia/mcp55/early_setup_car.c"
82 #include "cpu/amd/car/post_cache_as_ram.c"
83 #include "cpu/amd/model_fxx/init_cpus.c"
84 #include "cpu/amd/model_fxx/fidvid.c"
85 #include "northbridge/amd/amdk8/early_ht.c"
87 static void sio_setup(void)
92 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
94 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
96 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
98 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
100 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
102 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
105 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
107 static const uint16_t spd_addr[] = {
116 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
117 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
119 unsigned bsp_apicid = 0;
121 if (!cpu_init_detectedx && boot_cpu()) {
122 /* Nothing special needs to be done to find bus 0. */
123 /* Allow the HT devices to be found. */
124 enumerate_ht_chain();
129 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
131 /* FIXME: This should be part of the Super I/O code/config. */
132 pnp_enter_ext_func_mode(SERIAL_DEV);
133 /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
134 pnp_write_config(SERIAL_DEV, 0x24, 0);
135 w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
136 pnp_exit_ext_func_mode(SERIAL_DEV);
138 setup_mb_resource_map();
140 report_bist_failure(bist); /* Halt upon BIST failure. */
142 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
143 print_debug("bsp_apicid=");
144 print_debug_hex8(bsp_apicid);
147 #if CONFIG_MEM_TRAIN_SEQ == 1
148 /* In BSP so could hold all AP until sysinfo is in RAM. */
149 set_sysinfo_in_ram(0);
152 setup_coherent_ht_domain(); /* Routing table and start other core0. */
153 wait_all_core0_started();
155 #if CONFIG_LOGICAL_CPUS == 1
156 /* It is said that we should start core1 after all core0 launched
157 * becase optimize_link_coherent_ht is moved out from
158 * setup_coherent_ht_domain, so here need to make sure last core0 is
159 * started, esp for two way system (there may be APIC ID conflicts in
163 wait_all_other_cores_started(bsp_apicid);
166 /* Set up chains and store link pair for optimization later. */
167 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
169 #if CONFIG_SET_FIDVID
171 msr_t msr = rdmsr(0xc0010042);
172 print_debug("begin msr fid, vid ");
173 print_debug_hex32(msr.hi);
174 print_debug_hex32(msr.lo);
178 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
179 init_fidvid_bsp(bsp_apicid);
181 msr_t msr = rdmsr(0xc0010042);
182 print_debug("end msr fid, vid ");
183 print_debug_hex32(msr.hi);
184 print_debug_hex32(msr.lo);
189 init_timer(); /* Need to use TMICT to synconize FID/VID. */
191 needs_reset |= optimize_link_coherent_ht();
192 needs_reset |= optimize_link_incoherent_ht(sysinfo);
193 needs_reset |= mcp55_early_setup_x();
195 /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
197 print_info("ht reset -\n");
200 allow_all_aps_stop(bsp_apicid);
202 /* It's the time to set ctrl in sysinfo now. */
203 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
207 /* All AP stopped? */
209 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
211 /* bsp switch stack to RAM and copy sysinfo RAM now. */