2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/pci.h>
27 #include <cpu/amd/amdk8_sysconf.h>
29 extern unsigned char bus_mcp55[8]; // 1
30 extern unsigned apicid_mcp55;
32 static void *smp_write_config_table(void *v)
34 struct mp_config_table *mc;
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 mptable_init(mc, LAPIC_ADDR);
42 smp_write_processors(mc);
47 mptable_write_buses(mc, NULL, &bus_isa);
49 /* I/O APICs: APIC ID Version State Address */
55 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
57 res = find_resource(dev, PCI_BASE_ADDRESS_1);
59 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
62 pci_write_config32(dev, 0x7c, dword);
65 pci_write_config32(dev, 0x80, dword);
68 pci_write_config32(dev, 0x84, dword);
72 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
74 /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22
84 for (j = 7; j >= 2; j--) {
87 for (i = 0; i < 4; i++)
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2) | i, apicid_mcp55, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
91 for (j = 0; j < 2; j++) {
92 for (i = 0; i < 4; i++)
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06 + j) << 2) | i, apicid_mcp55, 0x10 + (2 + i + j) % 4);
96 /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
97 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
98 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
100 /* There is no extension information... */
102 /* Compute the checksums. */
104 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
105 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
106 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
107 mc, smp_next_mpe_entry(mc));
108 return smp_next_mpe_entry(mc);
111 unsigned long write_smp_table(unsigned long addr)
114 v = smp_write_floating_table(addr);
115 return (unsigned long)smp_write_config_table(v);