2 ## This file is part of the LinuxBIOS project.
4 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default ROM_SECTION_SIZE = FAILOVER_SIZE
23 default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
26 default ROM_SECTION_SIZE = FALLBACK_SIZE
27 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
29 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
30 default ROM_SECTION_OFFSET = 0
34 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
35 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
36 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
37 default XIP_ROM_SIZE = 65536
40 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
53 if HAVE_MP_TABLE object mptable.o end
54 if HAVE_PIRQ_TABLE object irq_tables.o end
59 makerule ./cache_as_ram_auto.o
60 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
61 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
64 makerule ./cache_as_ram_auto.inc
65 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
66 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
67 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
68 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
75 if CONFIG_AP_CODE_IN_CAR
77 depends "$(MAINBOARD)/apc_auto.c option_table.h"
78 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
80 ldscript /arch/i386/init/ldscript_apc.lb
86 mainboardinit cpu/x86/16bit/entry16.inc
87 ldscript /cpu/x86/16bit/entry16.lds
91 mainboardinit cpu/x86/16bit/entry16.inc
92 ldscript /cpu/x86/16bit/entry16.lds
96 mainboardinit cpu/x86/32bit/entry32.inc
100 ldscript /cpu/x86/32bit/entry32.lds
103 ldscript /cpu/amd/car/cache_as_ram.lds
107 if HAVE_FAILOVER_BOOT
108 if USE_FAILOVER_IMAGE
109 mainboardinit cpu/x86/16bit/reset16.inc
110 ldscript /cpu/x86/16bit/reset16.lds
112 mainboardinit cpu/x86/32bit/reset32.inc
113 ldscript /cpu/x86/32bit/reset32.lds
116 if USE_FALLBACK_IMAGE
117 mainboardinit cpu/x86/16bit/reset16.inc
118 ldscript /cpu/x86/16bit/reset16.lds
120 mainboardinit cpu/x86/32bit/reset32.inc
121 ldscript /cpu/x86/32bit/reset32.lds
125 mainboardinit southbridge/nvidia/mcp55/id.inc
126 ldscript /southbridge/nvidia/mcp55/id.lds
128 # ROMSTRAP table for MCP55.
129 if HAVE_FAILOVER_BOOT
130 if USE_FAILOVER_IMAGE
131 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
132 ldscript /southbridge/nvidia/mcp55/romstrap.lds
135 if USE_FALLBACK_IMAGE
136 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
137 ldscript /southbridge/nvidia/mcp55/romstrap.lds
142 mainboardinit cpu/amd/car/cache_as_ram.inc
145 if HAVE_FAILOVER_BOOT
146 if USE_FAILOVER_IMAGE
148 ldscript /arch/i386/lib/failover_failover.lds
152 if USE_FALLBACK_IMAGE
154 ldscript /arch/i386/lib/failover.lds
161 initobject cache_as_ram_auto.o
163 mainboardinit ./cache_as_ram_auto.inc
171 chip northbridge/amd/amdk8/root_complex # Root complex
172 device apic_cluster 0 on # APIC cluster
173 chip cpu/amd/socket_AM2 # CPU
174 device apic 0 on end # APIC
177 device pci_domain 0 on # PCI domain
178 chip northbridge/amd/amdk8 # Northbridge / mc0
180 # Devices on link 0, link 0 == LDT 0
181 chip southbridge/nvidia/mcp55 # Southbridge
182 device pci 0.0 on end # HT
183 device pci 1.0 on # LPC
184 chip superio/winbond/w83627ehg # Super I/O
185 device pnp 4e.0 on # Floppy
190 device pnp 4e.1 on # Parallel port
194 device pnp 4e.2 on # Com1
198 device pnp 4e.3 on # Com2 / IrDA
202 device pnp 4e.5 on # PS/2 keyboard
205 irq 0x70 = 1 # PS/2 keyboard IRQ
206 irq 0x72 = 12 # PS/2 mouse IRQ
208 device pnp 4e.6 off # Serial flash interface
211 device pnp 4e.7 off # GPIO1/6, game port, MIDI port
212 # io 0x60 = 0x220 # Datasheet: 0x201
213 # io 0x62 = 0x300 # Datasheet: 0x330
216 device pnp 4e.8 off # WDTO#, PLED
218 device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
220 device pnp 4e.a off # ACPI
222 device pnp 4e.b on # HWM (for lm-sensors)
227 device pci 1.1 on # SM 0
228 chip drivers/generic/generic # DIMM 0-0-0
231 chip drivers/generic/generic # DIMM 0-0-1
234 chip drivers/generic/generic # DIMM 0-1-0
237 chip drivers/generic/generic # DIMM 0-1-1
241 # chip drivers/generic/generic # DIMM 1-0-0
242 # device i2c 54 on end
244 # chip drivers/generic/generic # DIMM 1-0-1
245 # device i2c 55 on end
247 # chip drivers/generic/generic # DIMM 1-1-0
248 # device i2c 56 on end
250 # chip drivers/generic/generic # DIMM 1-1-1
251 # device i2c 57 on end
254 # TODO: Check if the stuff below is correct / needed.
255 device pci 1.1 on # SM 1
256 # PCI device SMBus address will depend on addon PCI device,
257 # do we need to scan_smbus_bus?
259 # chip drivers/generic/generic # PCIXA Slot1
260 # device i2c 50 on end
262 # chip drivers/generic/generic # PCIXB Slot1
263 # device i2c 51 on end
265 # chip drivers/generic/generic # PCIXB Slot2
266 # device i2c 52 on end
268 # chip drivers/generic/generic # PCI Slot1
269 # device i2c 53 on end
271 # chip drivers/generic/generic # Master MCP55 PCI-E
272 # device i2c 54 on end
274 # chip drivers/generic/generic # Slave MCP55 PCI-E
275 # device i2c 55 on end
277 chip drivers/generic/generic # MAC EEPROM
281 device pci 2.0 on end # USB 1.1
282 device pci 2.1 on end # USB 2
283 device pci 4.0 on end # IDE
284 device pci 5.0 on end # SATA 0
285 device pci 5.1 on end # SATA 1
286 device pci 5.2 off end # SATA 2 (N/A on this board)
287 device pci 6.0 on end # PCI
288 device pci 6.1 on end # AZA (HD Audio)
289 device pci 8.0 on end # NIC
290 device pci 9.0 off end # NIC (N/A on this board)
291 device pci a.0 off end # PCI E 5 (N/A on this board?)
292 device pci b.0 on end # PCI E 4
293 device pci c.0 on end # PCI E 3
294 device pci d.0 on end # PCI E 2
295 device pci e.0 on end # PCI E 1
296 device pci f.0 on end # PCI E 0
297 register "ide0_enable" = "1"
298 register "sata0_enable" = "1"
299 register "sata1_enable" = "1"
300 # TODO: Check the two lines below.
301 register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
302 register "mac_eeprom_addr" = "0x51"
305 device pci 18.0 on end # Link 1
306 device pci 18.0 on end
307 device pci 18.1 on end
308 device pci 18.2 on end
309 device pci 18.3 on end
314 # chip drivers/generic/debug
315 # device pnp 0.0 off end # chip name
316 # device pnp 0.1 on end # pci_regs_all
317 # device pnp 0.2 on end # mem
318 # device pnp 0.3 off end # cpuid
319 # device pnp 0.4 on end # smbus_regs_all
320 # device pnp 0.5 off end # dual core msr
321 # device pnp 0.6 off end # cache size
322 # device pnp 0.7 off end # tsc
323 # device pnp 0.8 off end # io
324 # device pnp 0.9 off end # io