2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <console/console.h>
26 #include <arch/smp/mpspec.h>
27 #include <device/pci.h>
31 #include <cpu/amd/amdk8_sysconf.h>
33 extern unsigned char bus_isa;
34 extern unsigned char bus_ck804[6];
35 extern unsigned apicid_ck804;
37 extern unsigned bus_type[256];
39 extern void get_bus_conf(void);
41 void *smp_write_config_table(void *v)
43 static const char sig[4] = "PCMP";
44 static const char oem[8] = "MSI ";
45 static const char productid[12] = "MS7135 ";
46 struct mp_config_table *mc;
52 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
53 memset(mc, 0, sizeof(*mc));
55 memcpy(mc->mpc_signature, sig, sizeof(sig));
56 mc->mpc_length = sizeof(*mc); /* initially just the header */
58 mc->mpc_checksum = 0; /* not yet computed */
59 memcpy(mc->mpc_oem, oem, sizeof(oem));
60 memcpy(mc->mpc_productid, productid, sizeof(productid));
63 mc->mpc_entry_count = 0; /* No entries yet... */
64 mc->mpc_lapic = LAPIC_ADDR;
69 smp_write_processors(mc);
75 /* define numbers for pci and isa bus */
76 for (bus_num = 0; bus_num < 256; bus_num++) {
77 if (bus_type[bus_num])
78 smp_write_bus(mc, bus_num, "PCI ");
80 smp_write_bus(mc, bus_isa, "ISA ");
83 /* I/O APICs: APIC ID Version State Address*/
89 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
91 res = find_resource(dev, PCI_BASE_ADDRESS_1);
93 smp_write_ioapic(mc, apicid_ck804, 0x11,
97 /* Initialize interrupt mapping */
99 /* copied from stock bios */
100 /*0x01800500,0x1800d509,0x00520d08*/
102 /* if this register is what i think it is ... */
104 pci_write_config32(dev, 0x7c, dword);
107 pci_write_config32(dev, 0x80, dword);
110 pci_write_config32(dev, 0x84, dword);
115 /* Now, assemble the table. */
117 smp_write_intsrc(mc, mp_ExtINT,
118 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
119 bus_isa, 0x0, apicid_ck804, 0x0);
121 #define ISA_INT(intr, pin) \
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, \
123 bus_isa, (intr), apicid_ck804, (pin))
140 #define PCI_INT(bus, dev, fn, pin) \
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
142 bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin))
145 // Onboard ck804 smbus
146 PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */
150 PCI_INT(0, sbdn+2, 0, 23);
151 PCI_INT(0, sbdn+2, 1, 23);
153 // Onboard ck804 AC-97
154 PCI_INT(0, sbdn+4, 0, 23);
156 // Onboard ck804 SATA 0
157 PCI_INT(0, sbdn+7, 0, 20);
159 // Onboard ck804 SATA 1
160 PCI_INT(0, sbdn+8, 0, 21);
163 PCI_INT(0, sbdn+10, 0, 22);
167 PCI_INT(1, 0, 0, 16);
168 PCI_INT(1, 0, 1, 17);
171 PCI_INT(1, 7, 0, 17);
172 PCI_INT(1, 7, 1, 18);
173 PCI_INT(1, 7, 2, 19);
174 PCI_INT(1, 7, 3, 16);
176 PCI_INT(1, 8, 0, 18);
177 PCI_INT(1, 8, 1, 19);
178 PCI_INT(1, 8, 2, 16);
179 PCI_INT(1, 8, 3, 17);
181 PCI_INT(1, 9, 0, 19);
182 PCI_INT(1, 9, 1, 16);
183 PCI_INT(1, 9, 2, 17);
184 PCI_INT(1, 9, 3, 18);
188 PCI_INT(2, 0, 0, 19);
190 PCI_INT(2, 0, 1, 16);
191 PCI_INT(2, 0, 2, 17);
192 PCI_INT(2, 0, 3, 18);
194 /* PCI-E x16 port */ /* XXX fix me ? */
195 PCI_INT(3, 0, 0, 18);
197 PCI_INT(3, 0, 1, 19);
198 PCI_INT(3, 0, 2, 16);
199 PCI_INT(3, 0, 3, 17);
201 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
202 smp_write_lintsrc(mc, mp_ExtINT,
203 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
204 bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
205 smp_write_lintsrc(mc, mp_NMI,
206 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
207 bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
209 /* There is no extension information... */
211 /* Compute the checksums */
213 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
214 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
215 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
216 mc, smp_next_mpe_entry(mc));
217 return smp_next_mpe_entry(mc);
220 unsigned long write_smp_table(unsigned long addr)
223 v = smp_write_floating_table(addr);
224 return (unsigned long)smp_write_config_table(v);