2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <console/console.h>
26 #include <arch/smp/mpspec.h>
27 #include <device/pci.h>
30 #include <cpu/amd/amdk8_sysconf.h>
32 extern unsigned char bus_ck804[6];
33 extern unsigned apicid_ck804;
35 static void *smp_write_config_table(void *v)
37 struct mp_config_table *mc;
44 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
46 mptable_init(mc, LAPIC_ADDR);
48 smp_write_processors(mc);
49 mptable_write_buses(mc, NULL, &bus_isa);
51 /* I/O APICs: APIC ID Version State Address*/
57 dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
59 res = find_resource(dev, PCI_BASE_ADDRESS_1);
61 smp_write_ioapic(mc, apicid_ck804, 0x11,
65 /* Initialize interrupt mapping */
67 /* copied from stock bios */
68 /*0x01800500,0x1800d509,0x00520d08*/
71 pci_write_config32(dev, 0x7c, dword);
74 pci_write_config32(dev, 0x80, dword);
77 pci_write_config32(dev, 0x84, dword);
82 /* Now, assemble the table. */
83 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
85 #define PCI_INT(bus, dev, fn, pin) \
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
87 bus_ck804[bus], (((dev)<<2)|(fn)), apicid_ck804, (pin))
90 // Onboard ck804 smbus
91 PCI_INT(0, sbdn+1, 1, 10); /* (this seems odd, how to test?) */
95 PCI_INT(0, sbdn+2, 0, 23);
96 PCI_INT(0, sbdn+2, 1, 23);
98 // Onboard ck804 AC-97
99 PCI_INT(0, sbdn+4, 0, 23);
101 // Onboard ck804 SATA 0
102 PCI_INT(0, sbdn+7, 0, 20);
104 // Onboard ck804 SATA 1
105 PCI_INT(0, sbdn+8, 0, 21);
108 PCI_INT(0, sbdn+10, 0, 22);
112 PCI_INT(1, 0, 0, 16);
113 PCI_INT(1, 0, 1, 17);
116 PCI_INT(1, 7, 0, 17);
117 PCI_INT(1, 7, 1, 18);
118 PCI_INT(1, 7, 2, 19);
119 PCI_INT(1, 7, 3, 16);
121 PCI_INT(1, 8, 0, 18);
122 PCI_INT(1, 8, 1, 19);
123 PCI_INT(1, 8, 2, 16);
124 PCI_INT(1, 8, 3, 17);
126 PCI_INT(1, 9, 0, 19);
127 PCI_INT(1, 9, 1, 16);
128 PCI_INT(1, 9, 2, 17);
129 PCI_INT(1, 9, 3, 18);
133 PCI_INT(2, 0, 0, 19);
135 PCI_INT(2, 0, 1, 16);
136 PCI_INT(2, 0, 2, 17);
137 PCI_INT(2, 0, 3, 18);
139 /* PCI-E x16 port */ /* XXX fix me ? */
140 PCI_INT(3, 0, 0, 18);
142 PCI_INT(3, 0, 1, 19);
143 PCI_INT(3, 0, 2, 16);
144 PCI_INT(3, 0, 3, 17);
146 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
147 mptable_lintsrc(mc, bus_ck804[0]);
149 /* There is no extension information... */
151 /* Compute the checksums */
152 return mptable_finalize(mc);
155 unsigned long write_smp_table(unsigned long addr)
158 v = smp_write_floating_table(addr, 0);
159 return (unsigned long)smp_write_config_table(v);