2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 /* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */
27 /* This is probably not right, feel free to fix this if you don't want
31 #include <console/console.h>
32 #include <device/pci.h>
35 #include <arch/pirq_routing.h>
36 #include <cpu/amd/amdk8_sysconf.h>
38 extern unsigned char bus_isa;
39 extern unsigned char bus_ck804[6];
43 * Add one line to IRQ table.
45 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
46 uint8_t devfn, uint8_t link0, uint16_t bitmap0,
47 uint8_t link1, uint16_t bitmap1, uint8_t link2,
48 uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
49 uint8_t slot, uint8_t rfu)
52 pirq_info->devfn = devfn;
53 pirq_info->irq[0].link = link0;
54 pirq_info->irq[0].bitmap = bitmap0;
55 pirq_info->irq[1].link = link1;
56 pirq_info->irq[1].bitmap = bitmap1;
57 pirq_info->irq[2].link = link2;
58 pirq_info->irq[2].bitmap = bitmap2;
59 pirq_info->irq[3].link = link3;
60 pirq_info->irq[3].bitmap = bitmap3;
61 pirq_info->slot = slot;
66 * Create the IRQ routing table.
67 * Values are derived from getpir generated code.
69 unsigned long write_pirq_routing_table(unsigned long addr)
72 struct irq_routing_table *pirq;
73 struct irq_info *pirq_info;
81 /* get_bus_conf() will find out all bus num and apic that share with
82 * mptable.c and mptable.c
87 /* Align the table to be 16 byte aligned. */
91 /* This table must be betweeen 0xf0000 & 0x100000 */
92 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
94 pirq = (void *)(addr);
95 v = (uint8_t *) (addr);
97 pirq->signature = PIRQ_SIGNATURE;
98 pirq->version = PIRQ_VERSION;
100 pirq->rtr_bus = bus_ck804[0];
101 pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
103 pirq->exclusive_irqs = 0x828;
105 pirq->rtr_vendor = 0x10de;
106 pirq->rtr_device = 0x005c;
108 pirq->miniport_data = 0;
110 memset(pirq->rfu, 0, sizeof(pirq->rfu));
112 pirq_info = (void *)(&pirq->checksum + 1);
116 write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
117 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
122 write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
123 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
128 write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
129 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
134 write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0,
135 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8,
141 for (i = 0; i < 3; i++) {
142 write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
143 ((i + 0) % 4) + 1, 0xdeb8,
144 ((i + 1) % 4) + 1, 0xdeb8,
145 ((i + 2) % 4) + 1, 0xdeb8,
146 ((i + 3) % 4) + 1, 0xdeb8, i, 0);
152 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
153 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
158 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
159 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
164 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
165 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
170 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1,
171 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
175 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
176 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
180 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
181 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
185 write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1,
186 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
190 pirq->size = 32 + 16 * slot_num;
192 for (i = 0; i < pirq->size; i++)
195 sum = pirq->checksum - sum;
197 if (sum != pirq->checksum) {
198 pirq->checksum = sum;
201 printk(BIOS_INFO, "done.\n");
204 unsigned char irq[4];
210 /* Bus, device, slots IRQs for {A,B,C,D}. */
212 irq[0] = 10; /* SMBus */ /* test me */
213 pci_assign_irqs(bus_ck804[0], 1, irq);
215 irq[0] = 10; /* USB */
217 pci_assign_irqs(bus_ck804[0], 2, irq);
219 irq[0] = 10; /* AC97 */
221 pci_assign_irqs(bus_ck804[0], 4, irq);
223 irq[0] = 11; /* SATA */
224 pci_assign_irqs(bus_ck804[0], 7, irq);
226 irq[0] = 5; /* SATA */
227 pci_assign_irqs(bus_ck804[0], 8, irq);
229 irq[0] = 10; /* Ethernet */
230 pci_assign_irqs(bus_ck804[0], 10, irq);
235 irq[0] = 5; /* PCI E1 - x1 */
236 pci_assign_irqs(bus_ck804[2], 0, irq);
238 irq[0] = 11; /* PCI E2 - x16 */
239 pci_assign_irqs(bus_ck804[3], 0, irq);
241 /* AGP-on-PCI "AGR" ignored */
243 irq[0] = 10; /* PCI1 */
247 pci_assign_irqs(bus_ck804[1], 7, irq);
249 irq[0] = 11; /* PCI2 */
253 pci_assign_irqs(bus_ck804[1], 8, irq);
255 irq[0] = 5; /* PCI3 */
259 pci_assign_irqs(bus_ck804[1], 9, irq);
262 return (unsigned long)pirq_info;