11 uses HAVE_OPTION_TABLE
12 uses CONFIG_SANDPOINT_ALTIMUS
14 uses DEFAULT_CONSOLE_LOGLEVEL
16 uses CONFIG_CHIP_CONFIGURE
18 uses CONFIG_CONSOLE_SERIAL8250
21 uses CONFIG_FS_PAYLOAD
23 uses CONFIG_FS_ISO9660
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_PRECOMPRESSED_PAYLOAD
32 uses _EXCEPTION_VECTORS
42 uses MAINBOARD_PART_NUMBER
43 uses COREBOOT_EXTRA_VERSION
52 default ISA_IO_BASE=0xfe000000
53 default ISA_MEM_BASE=0xfd000000
54 default PCIC0_CFGADDR=0xfec00000
55 default PCIC0_CFGDATA=0xfee00000
56 default PNP_CFGADDR=0x15c
57 default PNP_CFGDATA=0x15d
58 default _IO_BASE=ISA_IO_BASE
61 ## The default compiler
63 default CC="$(CROSS_COMPILE)gcc"
65 ## use a cross compiler
66 #default CROSS_COMPILE="powerpc-eabi-"
67 #default CROSS_COMPILE="ppc_74xx-"
69 ## Use stage 1 initialization code
70 default CONFIG_USE_INIT=1
72 ## Use static configuration
73 default CONFIG_CHIP_CONFIGURE=1
75 ## We don't use compressed image
76 default CONFIG_COMPRESS=0
78 ## Turn off POST codes
81 ## Enable serial console
82 default DEFAULT_CONSOLE_LOGLEVEL=8
83 default CONFIG_CONSOLE_SERIAL8250=1
84 default TTYS0_BASE=0x3f8
86 ## Load payload using filo
88 default CONFIG_FS_PAYLOAD=1
89 default CONFIG_FS_EXT2=1
90 default CONFIG_FS_ISO9660=1
91 default CONFIG_FS_FAT=1
92 default AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
94 # coreboot must fit into 128KB
95 default ROM_IMAGE_SIZE=131072
96 default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE}
97 default PAYLOAD_SIZE=262144
99 # Set stack and heap sizes (stage 2)
100 default STACK_SIZE=0x10000
101 default HEAP_SIZE=0x10000
103 # Sandpoint Demo Board
105 default _ROMBASE=0xfff00000
107 ## Sandpoint reset vector
108 default _RESET=_ROMBASE+0x100
110 ## Exception vectors (other than reset vector)
111 default _EXCEPTION_VECTORS=_RESET+0x100
113 ## Start of coreboot in the boot rom
114 ## = _RESET + exeception vector table size
115 default _ROMSTART=_RESET+0x3100
117 ## Coreboot C code runs at this location in RAM
118 default _RAMBASE=0x00100000
119 default _RAMSTART=0x00100000
126 default CONFIG_ROMFS=0