2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
23 ## XIP_ROM_SIZE must be a power of 2.
24 default XIP_ROM_SIZE = 64 * 1024
25 include /config/nofailovercalculation.lb
28 ## Set all of the defaults for an x86 architecture
33 ## Build the objects we have code for in this directory.
42 # compile cache_as_ram.c to auto.inc
43 makerule ./cache_as_ram_auto.inc
44 depends "$(MAINBOARD)/cache_as_ram_auto.c"
45 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
46 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
47 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
51 ## Build our 16 bit and 32 bit coreboot entry code
53 mainboardinit cpu/x86/16bit/entry16.inc
54 mainboardinit cpu/x86/32bit/entry32.inc
55 ldscript /cpu/x86/16bit/entry16.lds
56 ldscript /cpu/x86/32bit/entry32.lds
59 ## Build our reset vector (This is where coreboot is entered)
62 mainboardinit cpu/x86/16bit/reset16.inc
63 ldscript /cpu/x86/16bit/reset16.lds
65 mainboardinit cpu/x86/32bit/reset32.inc
66 ldscript /cpu/x86/32bit/reset32.lds
69 ### Should this be in the northbridge code?
70 #not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
73 ## Include an ID string (For safe flashing)
75 mainboardinit arch/i386/lib/id.inc
76 ldscript /arch/i386/lib/id.lds
79 ### This is the early phase of coreboot startup.
80 ### Things are delicate and we test to see if we should
81 ### failover to another image.
84 ldscript /arch/i386/lib/failover.lds
85 # mainboardinit ./failover.inc
89 ### O.k. We aren't just an intermediary anymore!
95 mainboardinit cpu/x86/fpu/enable_fpu.inc
97 mainboardinit cpu/amd/model_lx/cache_as_ram.inc
98 mainboardinit ./cache_as_ram_auto.inc
101 ## Include the secondary configuration files
106 # See also SMC_CONFIG in cache_as_ram_auto.c.
107 # Bit0 turns off Live LED, bit1 switches Com1 to RS485, bit2 same for Com2.
108 register "sio_gp1x_config" = "0x01"
110 chip northbridge/amd/lx
111 device pci_domain 0 on
112 device pci 1.0 on end # Northbridge
113 device pci 1.1 on end # Graphics
114 device pci 1.2 on end # AES
115 chip southbridge/amd/cs5536
116 # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
117 # SIRQ Mode = Active(Quiet) mode. Save power....
118 # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
119 # UARTs, etc IRQs. OK
120 register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
121 register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
122 register "lpc_serirq_mode" = "1"
123 register "enable_gpio_int_route" = "0x0D0C0700"
124 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
125 register "enable_USBP4_device" = "0" # 0:host, 1:device
126 register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
127 register "com1_enable" = "0"
128 register "com1_address" = "0x3E8"
129 register "com1_irq" = "6"
130 register "com2_enable" = "0"
131 register "com2_address" = "0x2E8"
132 register "com2_irq" = "6"
133 register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
134 register "unwanted_vpci[1]" = "0" # End of list has a zero
135 device pci 8.0 on end # Slot4
136 device pci 9.0 on end # Slot3
137 device pci a.0 on end # Slot2
138 device pci b.0 on end # Slot1
139 device pci c.0 on end # IT8888
140 device pci e.0 on end # Ethernet
141 device pci f.0 on # ISA Bridge
142 chip superio/ite/it8712f
143 device pnp 2e.0 off # Floppy
148 device pnp 2e.1 on # Com1
152 device pnp 2e.2 on # Com2
156 device pnp 2e.3 on # Parallel port
160 device pnp 2e.4 on # EC
165 device pnp 2e.5 on # PS/2 keyboard
170 device pnp 2e.6 on # PS/2 mouse
173 device pnp 2e.7 on # GPIO
177 device pnp 2e.8 off # MIDI
181 device pnp 2e.9 off # Game port
184 device pnp 2e.a off end # CIR
187 device pci f.2 on end # IDE
188 device pci f.3 off end # Audio
189 device pci f.4 on end # OHCI
190 device pci f.5 on end # EHCI
193 # APIC cluster is late CPU init.
194 device apic_cluster 0 on
195 chip cpu/amd/model_lx