2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
7 #include "pc80/serial.c"
8 #include "console/console.c"
9 #include "lib/ramtest.c"
10 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
11 #include "cpu/x86/bist.h"
12 #include "cpu/x86/msr.h"
13 #include <cpu/amd/gx2def.h>
15 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
17 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
18 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
19 #include "northbridge/amd/gx2/raminit.h"
21 /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
22 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
25 /* 1. Initialize GLMC registers base on SPD values,
26 * Hard coded as XpressROM for now */
27 //print_debug("sdram_enable step 1\n");
28 msr = rdmsr(0x20000018);
31 wrmsr(0x20000018, msr);
33 msr = rdmsr(0x20000019);
36 wrmsr(0x20000019, msr);
40 #include "northbridge/amd/gx2/raminit.c"
41 #include "lib/generic_sdram.c"
43 #define PLLMSRhi 0x00000226
44 #define PLLMSRlo 0x00000008
45 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
46 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
47 #include "northbridge/amd/gx2/pll_reset.c"
48 #include "cpu/amd/model_gx2/cpureginit.c"
49 #include "cpu/amd/model_gx2/syspreinit.c"
50 static void msr_init(void)
52 __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
54 __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
55 __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
56 __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
57 __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
58 __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
59 __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
61 __builtin_wrmsr(0x10000080, 0x3, 0x0);
63 __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
64 __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
65 __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
66 __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
67 __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
68 __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
70 __builtin_wrmsr(0x50002001, 0x27, 0x0);
71 __builtin_wrmsr(0x4c002001, 0x1, 0x0);
74 static void main(unsigned long bist)
76 static const struct mem_controller memctrl [] = {
77 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
83 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
88 print_err("done cs5535 early\n");
90 print_err("done pll_reset\n");
93 print_err("done cpuRegInit\n");
95 sdram_initialize(1, memctrl);
97 print_err("Done sdram_initialize\n");
98 print_err("Disable watchdog\n");
99 outb( 0x87, 0x4E); //enter SuperIO configuration mode
104 print_debug_hex8(temp);
106 print_err("CAN NOT READ SUPERIO VID\n");
112 outb( 0x07, 0x4E); //enable logical device 9
116 outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
118 outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
119 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
120 print_debug_hex8(temp);print_debug(":");
123 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
124 print_debug_hex8(temp);print_debug("\n");
125 /* Check all of memory */
126 // ram_check(0, 16384);
127 ram_check(0x20000, 0x24000);
128 // ram_check(0x00000000, 640*1024);