3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
7 #include <console/console.h>
8 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
9 #include "cpu/x86/bist.h"
10 #include "cpu/x86/msr.h"
11 #include <cpu/amd/gx2def.h>
12 #include <cpu/amd/geode_post_code.h>
13 #include "southbridge/amd/cs5535/cs5535.h"
14 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
15 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
17 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
19 static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
20 0xFF, 0xFF, /* only values used by raminit.c are set */
21 [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
22 [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */
23 [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */
24 [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */
26 [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
28 [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
29 [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */
31 [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */
32 [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
34 [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */
35 [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
36 [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
38 [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
40 [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */
41 [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */
42 [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
43 [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */
44 [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */
45 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
46 [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
49 static inline int spd_read_byte(unsigned int device, unsigned int address)
52 return 0xFF; /* No DIMM1, don't even try. */
54 #if CONFIG_DEBUG_SMBUS
55 if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
56 print_err("ERROR: spd_read_byte(DIMM0, 0x");
57 print_err_hex8(address);
58 print_err(") returns 0xff\n");
62 /* Fake SPD ROM value */
63 return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
66 #include "northbridge/amd/gx2/raminit.h"
67 #include "northbridge/amd/gx2/pll_reset.c"
68 #include "northbridge/amd/gx2/raminit.c"
69 #include "lib/generic_sdram.c"
70 #include "cpu/amd/model_gx2/cpureginit.c"
71 #include "cpu/amd/model_gx2/syspreinit.c"
72 #include "cpu/amd/model_lx/msrinit.c"
74 void main(unsigned long bist)
76 static const struct mem_controller memctrl [] = {
77 {.channel0 = {DIMM0, DIMM1}}
83 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
88 print_err("done cs5535 early\n");
90 /* Halt if there was a built in self test failure */
91 report_bist_failure(bist);
94 print_err("done pll_reset\n");
97 print_err("done cpuRegInit\n");
99 sdram_initialize(1, memctrl);
101 print_err("Done sdram_initialize\n");
102 print_err("Disable watchdog\n");
103 outb( 0x87, 0x4E); //enter SuperIO configuration mode
108 print_debug_hex8(temp);
110 print_err("CAN NOT READ SUPERIO VID\n");
116 outb( 0x07, 0x4E); //enable logical device 9
120 outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
122 outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
123 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
124 print_debug_hex8(temp);print_debug(":");
127 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
128 print_debug_hex8(temp);print_debug("\n");
129 /* Check all of memory */
130 // ram_check(0, 16384);
131 ram_check(0x20000, 0x24000);
132 // ram_check(0x00000000, 640*1024);