2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <console/console.h>
23 #include <device/device.h>
25 #include <boot/tables.h>
29 #include "southbridge/intel/i82801gx/i82801gx.h"
30 #include "superio/nsc/pc87392/pc87392.h"
32 static void dlpc_write_register(int reg, int value)
38 static u8 dlpc_read_register(int reg)
44 static void dock_write_register(int reg, int value)
50 static u8 dock_read_register(int reg)
56 static void dlpc_gpio_set_mode(int port, int mode)
58 dlpc_write_register(0xf0, port);
59 dlpc_write_register(0xf1, mode);
62 static void dock_gpio_set_mode(int port, int mode, int irq)
64 dock_write_register(0xf0, port);
65 dock_write_register(0xf1, mode);
66 dock_write_register(0xf2, irq);
69 static void dlpc_gpio_init(void)
71 /* Select GPIO module */
72 dlpc_write_register(0x07, 0x07);
73 /* GPIO Base Address 0x1680 */
74 dlpc_write_register(0x60, 0x16);
75 dlpc_write_register(0x61, 0x80);
78 dlpc_write_register(0x30, 0x01);
80 dlpc_gpio_set_mode(0x00, 3);
81 dlpc_gpio_set_mode(0x01, 3);
82 dlpc_gpio_set_mode(0x02, 0);
83 dlpc_gpio_set_mode(0x03, 3);
84 dlpc_gpio_set_mode(0x04, 4);
85 dlpc_gpio_set_mode(0x20, 4);
86 dlpc_gpio_set_mode(0x21, 4);
87 dlpc_gpio_set_mode(0x23, 4);
94 /* Enable 14.318MHz CLK on CLKIN */
95 dlpc_write_register(0x29, 0xa0);
96 while(!(dlpc_read_register(0x29) & 0x10) && timeout--)
102 /* Select DLPC module */
103 dlpc_write_register(0x07, 0x19);
104 /* DLPC Base Address 0x164c */
105 dlpc_write_register(0x60, 0x16);
106 dlpc_write_register(0x61, 0x4c);
108 dlpc_write_register(0x30, 0x01);
114 while(!(inb(0x164c) & 8) && timeout--)
118 /* docking failed, disable DLPC switch */
120 dlpc_write_register(0x30, 0x00);
129 int dock_connect(void)
133 /* Assert D_PLTRST# */
136 /* Deassert D_PLTRST# */
139 /* startup 14.318MHz Clock */
140 dock_write_register(0x29, 0x06);
141 /* wait until clock is settled */
142 while(!(dock_read_register(0x29) & 0x08) && timeout--)
153 dock_write_register(0x24, 0x37);
155 /* PNF active HIGH */
156 dock_write_register(0x25, 0xa0);
159 dock_write_register(0x26, 0x01);
161 /* Enable GPIO IRQ to #SMI */
162 dock_write_register(0x28, 0x02);
165 dock_write_register(0x07, 0x07);
167 /* set base address */
168 dock_write_register(0x60, 0x16);
169 dock_write_register(0x61, 0x20);
172 dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE |
173 PC87392_GPIO_PIN_PULLUP, 0x00);
175 dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE |
176 PC87392_GPIO_PIN_PULLUP,
177 PC87392_GPIO_PIN_TRIGGERS_SMI);
179 dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00);
180 dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00);
181 dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00);
182 dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00);
183 dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00);
184 dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02);
186 dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE |
187 PC87392_GPIO_PIN_PULLUP,
188 PC87392_GPIO_PIN_TRIGGERS_SMI);
190 dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00);
191 dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00);
192 dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00);
193 dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
194 dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
195 dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
196 PC87392_GPIO_PIN_OE , 0x00);
198 dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
200 dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
201 PC87392_GPIO_PIN_OE, 0x00);
203 dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
204 PC87392_GPIO_PIN_OE, 0x00);
206 dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00);
207 dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00);
208 dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00);
209 dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00);
210 dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00);
211 dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00);
213 dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00);
214 dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00);
215 dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00);
216 dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00);
217 dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00);
219 dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP |
220 PC87392_GPIO_PIN_OE, 0x00);
222 dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00);
223 dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00);
226 dock_write_register(0x30, 0x01);
233 /* Enable USB and Ultrabay power */
238 void dock_disconnect(void)
240 /* disconnect LPC bus */
242 /* Assert PLTRST and DLPCPD */
246 int dock_present(void)
248 return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1);
251 int dock_ultrabay_device_present(void)
253 return inb(0x1621) & 0x02 ? 0 : 1;