2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
5 ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
7 ## This program is free software; you can redistribute it and/or
8 ## modify it under the terms of the GNU General Public License as
9 ## published by the Free Software Foundation; version 2 of
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 chip northbridge/intel/i945
25 device lapic_cluster 0 on
26 chip cpu/intel/socket_mFCPGA478
31 device pci_domain 0 on
32 device pci 00.0 on # Host bridge
33 subsystemid 0x17aa 0x2017
35 device pci 02.0 on # VGA controller
36 subsystemid 0x17aa 0x201a
38 device pci 02.1 on # display controller
39 subsystemid 0x17aa 0x201a
41 chip southbridge/intel/i82801gx
42 register "pirqa_routing" = "0x0b"
43 register "pirqb_routing" = "0x0b"
44 register "pirqc_routing" = "0x0b"
45 register "pirqd_routing" = "0x0b"
46 register "pirqe_routing" = "0x0b"
47 register "pirqf_routing" = "0x0b"
48 register "pirqg_routing" = "0x0b"
49 register "pirqh_routing" = "0x0b"
52 # 0 No effect (default)
53 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
54 # 2 SCI (if corresponding GPIO_EN bit is also set)
55 register "gpi13_routing" = "2"
56 register "gpi12_routing" = "1"
57 register "gpi8_routing" = "2"
59 register "sata_ahci" = "0x0"
61 register "gpe0_en" = "0x11000006"
62 register "alt_gp_smi_en" = "0x1000"
63 device pci 1b.0 on # Audio Cnotroller
64 subsystemid 0x17aa 0x2010
66 device pci 1c.0 on end # Ethernet
67 device pci 1c.1 on end # Atheros WLAN
68 device pci 1d.0 on # USB UHCI
69 subsystemid 0x17aa 0x200a
71 device pci 1d.1 on # USB UHCI
72 subsystemid 0x17aa 0x200a
74 device pci 1d.2 on # USB UHCI
75 subsystemid 0x17aa 0x200a
77 device pci 1d.3 on # USB UHCI
78 subsystemid 0x17aa 0x200a
80 device pci 1d.7 on # USB2 EHCI
81 subsystemid 0x17aa 0x200b
83 device pci 1f.0 on # PCI-LPC bridge
84 subsystemid 0x17aa 0x2009
86 device pnp ff.1 on # dummy
88 register "backlight_enable" = "0x01"
91 device pnp ff.2 on # dummy
98 register "config0" = "0xa6"
99 register "config1" = "0x05"
100 register "config2" = "0xa0"
101 register "config3" = "0x05"
103 register "beepmask0" = "0xfe"
104 register "beepmask1" = "0x96"
106 register "event2_enable" = "0xff"
107 register "event3_enable" = "0xff"
108 register "event4_enable" = "0xf4"
109 register "event5_enable" = "0x3c"
110 register "eventc_enable" = "0x3c"
112 register "wlan_enable" = "0x01"
113 register "trackpoint_enable" = "0x03"
115 chip superio/nsc/pc87382
116 device pnp 164e.2 on # IR
120 device pnp 164e.3 off # Serial Port
124 device pnp 164e.7 on # GPIO
128 device pnp 164e.19 on # DLPC
133 chip superio/nsc/pc87392
134 device pnp 2e.0 off #FDC
137 device pnp 2e.1 on # Parallel Port
142 device pnp 2e.2 off # Serial Port / IR
147 device pnp 2e.3 on # Serial Port
152 device pnp 2e.7 on # GPIO
156 device pnp 2e.a off # WDT
160 device pci 1f.1 on # IDE
161 subsystemid 0x17aa 0x200c
163 device pci 1f.2 on # SATA
164 subsystemid 0x17aa 0x200d
166 device pci 1f.3 on # SMBUS
167 subsystemid 0x17aa 0x200f
170 chip southbridge/ricoh/rl5c476