2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
28 #include <arch/romcc_io.h>
29 #include <device/pci_def.h>
30 #include <device/pnp_def.h>
31 #include <cpu/x86/lapic.h>
33 #include <pc80/mc146818rtc.h>
34 #include <console/console.h>
36 #include <cpu/x86/bist.h>
37 #include "northbridge/intel/i945/i945.h"
38 #include "northbridge/intel/i945/raminit.h"
39 #include "southbridge/intel/i82801gx/i82801gx.h"
42 void setup_ich7_gpios(void)
44 printk(BIOS_DEBUG, " GPIOS...");
63 outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
64 outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
65 outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
66 /* Output Control Registers */
67 outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
68 /* Input Control Registers */
69 outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
70 outl(0x000100f0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
71 outl(0x000000f1, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
72 outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
75 static void ich7_enable_lpc(void)
78 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
80 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
82 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
84 /* range 0x1600 - 0x167f */
85 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
86 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
88 /* range 0x15e0 - 0x10ef */
89 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
90 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
92 /* range 0x1680 - 0x169f */
93 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
94 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
97 static void early_superio_config(void)
100 device_t dev = PNP_DEV(0x2e, 3);
102 pnp_write_config(dev, 0x29, 0xa0);
104 while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--)
108 pnp_set_logical_device(dev);
109 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
110 pnp_set_enable(dev, 1);
113 static void rcba_config(void)
115 /* Set up virtual channel 0 */
116 RCBA32(0x0014) = 0x80000001;
117 RCBA32(0x001c) = 0x03128010;
119 /* Device 1f interrupt pin register */
120 RCBA32(0x3100) = 0x00001230;
121 RCBA32(0x3108) = 0x40004321;
123 /* PCIe Interrupts */
124 RCBA32(0x310c) = 0x00004321;
125 /* HD Audio Interrupt */
126 RCBA32(0x3110) = 0x00000002;
128 /* dev irq route register */
129 RCBA16(0x3140) = 0x1007;
130 RCBA16(0x3142) = 0x0076;
131 RCBA16(0x3144) = 0x3210;
132 RCBA16(0x3146) = 0x7654;
133 RCBA16(0x3148) = 0x0010;
136 RCBA8(0x31ff) = 0x03;
138 /* Enable upper 128bytes of CMOS */
139 RCBA32(0x3400) = (1 << 2);
141 /* Disable unused devices */
142 RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
143 RCBA32(0x3418) |= (1 << 0); // Required.
145 /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
146 RCBA32(0x1e84) = 0x00020001;
147 RCBA32(0x1e80) = 0x0000fe01;
149 /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
150 RCBA32(0x1e9c) = 0x000200f0;
151 RCBA32(0x1e98) = 0x000c0801;
154 static void early_ich7_init(void)
159 // program secondary mlt XXX byte?
160 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
162 // reset rtc power status
163 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
165 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
167 // usb transient disconnect
168 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
170 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
172 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
173 reg32 |= (1 << 29) | (1 << 17);
174 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
176 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
177 reg32 |= (1 << 31) | (1 << 27);
178 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
180 RCBA32(0x0088) = 0x0011d000;
181 RCBA16(0x01fc) = 0x060f;
182 RCBA32(0x01f4) = 0x86000040;
183 RCBA32(0x0214) = 0x10030549;
184 RCBA32(0x0218) = 0x00020504;
185 RCBA8(0x0220) = 0xc5;
186 reg32 = RCBA32(0x3410);
188 RCBA32(0x3410) = reg32;
189 reg32 = RCBA32(0x3430);
192 RCBA32(0x3430) = reg32;
193 RCBA32(0x3418) |= (1 << 0);
194 RCBA16(0x0200) = 0x2008;
195 RCBA8(0x2027) = 0x0d;
196 RCBA16(0x3e08) |= (1 << 7);
197 RCBA16(0x3e48) |= (1 << 7);
198 RCBA32(0x3e0e) |= (1 << 7);
199 RCBA32(0x3e4e) |= (1 << 7);
201 // next step only on ich7m b0 and later:
202 reg32 = RCBA32(0x2034);
203 reg32 &= ~(0x0f << 16);
205 RCBA32(0x2034) = reg32;
210 void main(unsigned long bist)
214 const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
220 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
222 pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
227 /* dock_init initializes the DLPC switch on
228 * thinpad side, so this is required even
231 if (!dlpc_init() && dock_present()) {
233 early_superio_config();
234 /* Set up the console */
238 i82801gx_enable_usbdebug(1);
239 early_usbdebug_init();
244 /* Halt if there was a built in self test failure */
245 report_bist_failure(bist);
247 if (MCHBAR16(SSKPD) == 0xCAFE) {
248 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
250 while (1) asm("hlt");
253 /* Perform some early chipset initialization required
254 * before RAM initialization can work
256 i945_early_initialization();
259 reg32 = inl(DEFAULT_PMBASE + 0x04);
260 printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
261 if (((reg32 >> 10) & 7) == 5) {
262 #if CONFIG_HAVE_ACPI_RESUME
263 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
265 /* Clear SLP_TYPE. This will break stage2 but
266 * we care for that when we get there.
268 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
271 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
275 /* Enable SPD ROMs and DDR-II DRAM */
278 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
279 dump_spd_registers();
282 sdram_initialize(boot_mode, spd_addrmap);
284 /* Perform some initialization that must run before stage2 */
287 /* This should probably go away. Until now it is required
288 * and mainboard specific
292 /* Chipset Errata! */
295 /* Initialize the internal PCIe links before we go into stage2 */
296 i945_late_initialization();
298 #if !CONFIG_HAVE_ACPI_RESUME
299 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
300 #if CONFIG_DEBUG_RAM_SETUP
301 sdram_dump_mchbar_registers();
304 /* This will not work if TSEG is in place! */
305 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
307 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
308 ram_check(0x00000000, 0x000a0000);
309 ram_check(0x00100000, tom);
315 MCHBAR16(SSKPD) = 0xCAFE;
317 #if CONFIG_HAVE_ACPI_RESUME
318 /* Start address of high memory tables */
319 unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
321 /* If there is no high memory area, we didn't boot before, so
322 * this is not a resume. In that case we just create the cbmem toc.
324 if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
325 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
327 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
328 * through stage 2. We could keep stuff like stack and heap in high tables
329 * memory completely, but that's a wonderful clean up task for another
332 if (resume_backup_memory)
333 memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
335 /* Magic for S3 resume */
336 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);