2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <arch/romcc_io.h>
24 #include <console/console.h>
25 #include <cpu/x86/smm.h>
26 #include "southbridge/intel/i82801gx/nvs.h"
27 #include "southbridge/intel/i82801gx/i82801gx.h"
28 #include <ec/acpi/ec.h>
32 #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */
33 /* The southbridge SMI handler checks whether gnvs has a
34 * valid pointer before calling the trap handler
36 extern global_nvs_t *gnvs;
38 static void mainboard_smm_init(void)
40 printk(BIOS_DEBUG, "initializing SMI\n");
41 /* Enable 0x1600/0x1600 register pair */
42 ec_set_bit(0x00, 0x05);
45 static void mainboard_smi_brightness_down(void)
48 if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
49 printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
50 *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0;
51 if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10)
52 *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10;
56 static void mainboard_smi_brightness_up(void)
59 if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
60 printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));
61 *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
62 if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
63 *(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
67 int mainboard_io_trap_handler(int smif)
69 static int smm_initialized;
71 if (!smm_initialized) {
77 case SMI_DOCK_CONNECT:
78 /* If there's an legacy I/O module present, we're not
79 * allowed to connect the Docking LPC Bus, as both Super I/O
80 * chips are using 0x2e as base address.
82 if (legacy_io_present())
85 if (!dock_connect()) {
86 /* set dock LED to indicate status */
90 /* blink dock LED to indicate failure */
96 case SMI_DOCK_DISCONNECT:
102 case SMI_BRIGHTNESS_UP:
103 mainboard_smi_brightness_up();
106 case SMI_BRIGHTNESS_DOWN:
107 mainboard_smi_brightness_down();
114 /* On success, the IO Trap Handler returns 1
115 * On failure, the IO Trap Handler returns a value != 1 */
119 static void mainboard_smi_handle_ec_sci(void)
121 u8 status = inb(EC_SC);
124 if (!(status & EC_SCI_EVT))
128 printk(BIOS_DEBUG, "EC event %02x\n", event);
133 mainboard_smi_brightness_up();
135 /* brightness down */
137 mainboard_smi_brightness_down();
145 mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
149 mainboard_io_trap_handler(SMI_DOCK_CONNECT);
156 void mainboard_smi_gpi(u16 gpi)
159 mainboard_smi_handle_ec_sci();
162 int mainboard_apm_cnt(u8 data)
164 u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
167 printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
173 case APM_CNT_ACPI_ENABLE:
174 /* use 0x1600/0x1604 to prevent races with userspace */
175 ec_set_ports(0x1604, 0x1600);
176 /* route H8SCI to SCI */
177 outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
178 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
181 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
183 case APM_CNT_ACPI_DISABLE:
184 /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
185 provide a EC query function */
186 ec_set_ports(0x66, 0x62);
187 /* route H8SCI# to SMI */
188 outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
189 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
192 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);