2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <console/console.h>
23 #include <device/device.h>
25 #include <boot/tables.h>
29 #include "superio/nsc/pc87384/pc87384.h"
30 #include "ec/acpi/ec.h"
31 #include "southbridge/intel/i82801gx/i82801gx.h"
33 static void dlpc_write_register(int reg, int value)
39 static u8 dlpc_read_register(int reg)
45 static void dock_write_register(int reg, int value)
51 static u8 dock_read_register(int reg)
57 static void dlpc_gpio_set_mode(int port, int mode)
59 dlpc_write_register(0xf0, port);
60 dlpc_write_register(0xf1, mode);
63 static void dock_gpio_set_mode(int port, int mode, int irq)
65 dock_write_register(0xf0, port);
66 dock_write_register(0xf1, mode);
67 dock_write_register(0xf2, irq);
70 static void dlpc_gpio_init(void)
72 /* Select GPIO module */
73 dlpc_write_register(0x07, 0x07);
74 /* GPIO Base Address 0x1680 */
75 dlpc_write_register(0x60, 0x16);
76 dlpc_write_register(0x61, 0x80);
79 dlpc_write_register(0x30, 0x01);
81 dlpc_gpio_set_mode(0x00, 3);
82 dlpc_gpio_set_mode(0x01, 3);
83 dlpc_gpio_set_mode(0x02, 0);
84 dlpc_gpio_set_mode(0x03, 3);
85 dlpc_gpio_set_mode(0x04, 4);
86 dlpc_gpio_set_mode(0x20, 4);
87 dlpc_gpio_set_mode(0x21, 4);
88 dlpc_gpio_set_mode(0x23, 4);
95 /* Enable 14.318MHz CLK on CLKIN */
96 dlpc_write_register(0x29, 0xa0);
97 while(!(dlpc_read_register(0x29) & 0x10) && timeout--)
103 /* Select DLPC module */
104 dlpc_write_register(0x07, 0x19);
105 /* DLPC Base Address 0x164c */
106 dlpc_write_register(0x60, 0x16);
107 dlpc_write_register(0x61, 0x4c);
109 dlpc_write_register(0x30, 0x01);
115 static int dock_superio_init(void)
118 /* startup 14.318MHz Clock */
119 dock_write_register(0x29, 0xa0);
120 /* wait until clock is settled */
121 while(!(dock_read_register(0x29) & 0x10) && timeout--)
127 /* set GPIO pins to Serial/Parallel Port
130 dock_write_register(0x22, 0xeb);
132 dock_write_register(0x07, PC87384_GPIO);
133 dock_write_register(0x60, 0x16);
134 dock_write_register(0x61, 0x20);
136 dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
137 PC87384_GPIO_PIN_PULLUP, 0x00);
139 dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
140 PC87384_GPIO_PIN_OE, 0x00);
142 dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
143 PC87384_GPIO_PIN_OE, 0x00);
145 dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
146 PC87384_GPIO_PIN_PULLUP, 0x00);
148 dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
149 PC87384_GPIO_PIN_PULLUP, 0x00);
151 dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
152 PC87384_GPIO_PIN_PULLUP, 0x00);
154 dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
155 PC87384_GPIO_PIN_PULLUP, 0x00);
157 dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
158 PC87384_GPIO_PIN_PULLUP, 0x00);
162 /* no GPIO events enabled for PORT0 */
164 /* clear GPIO events on PORT0 */
167 /* no GPIO events enabled for PORT1 */
170 /* clear GPIO events on PORT1*/
174 dock_write_register(0x30, 0x01);
178 int dock_connect(void)
186 while(!(inb(0x164c) & 8) && timeout--)
190 /* docking failed, disable DLPC switch */
192 dlpc_write_register(0x30, 0x00);
196 /* Assert D_PLTRST# */
199 /* Deassert D_PLTRST# */
203 return dock_superio_init();
206 void dock_disconnect(void)
208 /* disconnect LPC bus */
210 /* Assert PLTRST and DLPCPD */
214 int dock_present(void)
217 return inb(0x15ee) & 1;